lc3_realized
The LC3 Processor realized now in schematic capture in Digital, and hopefully soon in Verilog
Science Score: 44.0%
This score indicates how likely this project is to be science-related based on various indicators:
-
✓CITATION.cff file
Found CITATION.cff file -
✓codemeta.json file
Found codemeta.json file -
✓.zenodo.json file
Found .zenodo.json file -
○DOI references
-
○Academic publication links
-
○Academic email domains
-
○Institutional organization owner
-
○JOSS paper metadata
-
○Scientific vocabulary similarity
Low similarity (6.6%) to scientific vocabulary
Repository
The LC3 Processor realized now in schematic capture in Digital, and hopefully soon in Verilog
Basic Info
- Host: GitHub
- Owner: ucrdrk
- Language: Verilog
- Default Branch: main
- Size: 283 KB
Statistics
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
- Releases: 2
Metadata Files
README.md
LC3_realized
The LC3 Processor realized now in schematic capture in Digital, and hopefully soon in Verilog.
Usage
In Digital load the file lc3.dig. You might need to change the path for the hex and verilog. To change the path for the hex file loaded to initialize RAM go to Edit -> Settings -> Circuit specific settings. Under the Advanced tab go to "Program File" and navigate to where you cloned this repo and select the file lc3_os.hex. To change the path to the verilog for lc-pc.v, right click on module labeled PC with the type External File On the Basic tab go to the field "Program code" and navigate to where you cloned this repo and select the file lc-pc.v.
To run the program in lc3os.hex, press the play button. This will start the simulation, but not run the program. You can eitehr step throught each state of executing the program by continuously clicking the Clk clock or run the entire program by pressing the fast forward button next to the play button. The default program in lc3os.hex is the "Hello, World!" program which willopen the terminal and print the following:
``` Hello, World!
--- Halting the LC-3 --- ```
NOTE You will need to have iverilog installed on your computer because the PC is implemented using Verilog.
Owner
- Name: Allan Knight
- Login: ucrdrk
- Kind: user
- Company: UC Riverside
- Repositories: 1
- Profile: https://github.com/ucrdrk
Citation (CITATION.cff)
cff-version: 1.2.0
message: "If you use this software, please cite it as below."
authors:
- family-names: Knight
given-names: Allan
orcid: https://orcid.org/0000-0002-8419-3924
title: "LC-3 Realized"
version: 1.0.0
date-released: 2023-04-11
GitHub Events
Total
- Push event: 3
Last Year
- Push event: 3