https://github.com/autohdw/svet
SystemVerilog based Easy Testing Template
Science Score: 13.0%
This score indicates how likely this project is to be science-related based on various indicators:
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○CITATION.cff file
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✓codemeta.json file
Found codemeta.json file -
○.zenodo.json file
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○DOI references
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○Academic publication links
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○Academic email domains
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○Institutional organization owner
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○JOSS paper metadata
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○Scientific vocabulary similarity
Low similarity (0.6%) to scientific vocabulary
Last synced: 10 months ago
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JSON representation
Repository
SystemVerilog based Easy Testing Template
Basic Info
- Host: GitHub
- Owner: autohdw
- License: mit
- Default Branch: master
- Size: 1000 Bytes
Statistics
- Stars: 0
- Watchers: 0
- Forks: 0
- Open Issues: 0
- Releases: 0
Created about 2 years ago
· Last pushed about 2 years ago
Metadata Files
Readme
License
README.md
SVET
SystemVerilog based Easy Testing Template
Owner
- Name: Auto HDW
- Login: autohdw
- Kind: organization
- Email: contact@autohdw.com
- Website: https://autohdw.com
- Repositories: 8
- Profile: https://github.com/autohdw
LEADS Auto Hardware