https://github.com/caglayandokme/systemverilogexercises
This is a repo where I share the System Verilog exercises that I worked on. Contributions and suggestions are welcome
Science Score: 26.0%
This score indicates how likely this project is to be science-related based on various indicators:
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○CITATION.cff file
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✓codemeta.json file
Found codemeta.json file -
✓.zenodo.json file
Found .zenodo.json file -
○DOI references
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○Academic publication links
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○Academic email domains
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○Institutional organization owner
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○JOSS paper metadata
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○Scientific vocabulary similarity
Low similarity (2.0%) to scientific vocabulary
Keywords
digital-design
systemverilog
systemverilog-hdl
Last synced: 10 months ago
·
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Repository
This is a repo where I share the System Verilog exercises that I worked on. Contributions and suggestions are welcome
Basic Info
Statistics
- Stars: 3
- Watchers: 1
- Forks: 1
- Open Issues: 0
- Releases: 0
Topics
digital-design
systemverilog
systemverilog-hdl
Created about 5 years ago
· Last pushed about 5 years ago
Metadata Files
Readme
README.md
SystemVerilogExercises
This is a repo where I share the System Verilog exercises that I worked on. Related files are grouped with folders. Each module has its testbench file located at the same directory.
The repo is open to contributions and suggestions.
Owner
- Name: Caglayan DOKME
- Login: CaglayanDokme
- Kind: user
- Location: Ankara/Türkiye
- Company: Plan-S Satellite and Space Systems
- Website: linkedin.com/in/caglayandokme/
- Repositories: 2
- Profile: https://github.com/CaglayanDokme
GitHub Events
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Last Year
- Watch event: 2