https://github.com/caleb531/cache-simulator

A processor cache simulator for the MIPS architecture

https://github.com/caleb531/cache-simulator

Science Score: 26.0%

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  • Scientific vocabulary similarity
    Low similarity (8.4%) to scientific vocabulary

Keywords

cache mips processor processor-architecture python simulator

Keywords from Contributors

projection interactive archival turing-machine generic sequences observability autograding hacking shellcodes
Last synced: 5 months ago · JSON representation

Repository

A processor cache simulator for the MIPS architecture

Basic Info
Statistics
  • Stars: 39
  • Watchers: 2
  • Forks: 18
  • Open Issues: 0
  • Releases: 7
Topics
cache mips processor processor-architecture python simulator
Created about 10 years ago · Last pushed 8 months ago
Metadata Files
Readme License

README.md

Cache Simulator

Copyright 2015-2024 Caleb Evans
Released under the MIT license

tests Coverage Status

This program simulates a processor cache for the MIPS instruction set architecture. It can simulate all three fundamental caching schemes: direct-mapped, n-way set associative, and fully associative.

The program must be run from the command line and requires Python 3.4+ to run. Executing the program will run the simulation and print an ASCII table containing the details for each supplied word address, as well as the final contents of the cache.

For example, the following command simulates a 3-way set associative LRU cache, with 2 words per block. To see all examples and their respective outputs, see examples.txt.

```sh

3-way set associative (LRU; 2 words per block)

cache-simulator --cache-size 24 --num-blocks-per-set 3 --num-words-per-block 2 --word-addrs 3 180 43 2 191 88 190 14 181 44 186 253 ```

This produces the following output:

```

WordAddr BinAddr Tag Index Offset Hit/Miss

        3    0000 0011        00000           01            1         miss
      180    1011 0100        10110           10            0         miss
       43    0010 1011        00101           01            1         miss
        2    0000 0010        00000           01            0          HIT
      191    1011 1111        10111           11            1         miss
       88    0101 1000        01011           00            0         miss
      190    1011 1110        10111           11            0          HIT
       14    0000 1110        00001           11            0         miss
      181    1011 0101        10110           10            1          HIT
       44    0010 1100        00101           10            0         miss
      186    1011 1010        10111           01            0         miss
      253    1111 1101        11111           10            1         miss

                                 Cache

     00                  01                  10                  11

   88,89         2,3 42,43 186,187  180,181 44,45 252,253   190,191 14,15

```

Installing

You can install Cache Simulator via pip (ideally globally):

pip install cache-simulator

Command-line parameters

Required parameters

--cache-size

The size of the cache in words (recall that one word is four bytes in MIPS).

--word-addrs

One or more word addresses (separated by spaces), where each word address is a base-10 positive integer.

Optional parameters

--num-blocks-per-set

The program internally represents all cache schemes using a set associative cache. A value of 1 for this parameter (the default) implies a direct-mapped cache. A value other than 1 implies either a set associative or fully associative cache.

--num-words-per-block

The number of words to store for each block in the cache; the default value is 1.

--num-addr-bits

The number of bits used to represent each given word address; this value is reflected in the BinAddr column in the reference table. If omitted, the default value is the number of bits needed to represent the largest of the given word addresses.

--replacement-policy

The replacement policy to use for the cache. Accepted values are lru (Least Recently Used; the default) and mru (Most Recently Used).

Owner

  • Name: Caleb Evans
  • Login: caleb531
  • Kind: user
  • Location: Carlsbad, CA

Hi, I'm Caleb, a web developer who lives for Christ by building enjoyable apps and useful tools. I hope you are blessed by what I've made!

GitHub Events

Total
  • Release event: 1
  • Watch event: 2
  • Delete event: 3
  • Push event: 27
  • Fork event: 2
  • Create event: 5
Last Year
  • Release event: 1
  • Watch event: 2
  • Delete event: 3
  • Push event: 27
  • Fork event: 2
  • Create event: 5

Committers

Last synced: about 2 years ago

All Time
  • Total Commits: 134
  • Total Committers: 2
  • Avg Commits per committer: 67.0
  • Development Distribution Score (DDS): 0.022
Past Year
  • Commits: 7
  • Committers: 1
  • Avg Commits per committer: 7.0
  • Development Distribution Score (DDS): 0.0
Top Committers
Name Email Commits
Caleb Evans c****b@c****e 131
dependabot[bot] 4****] 3
Committer Domains (Top 20 + Academic)

Issues and Pull Requests

Last synced: 8 months ago

All Time
  • Total issues: 0
  • Total pull requests: 7
  • Average time to close issues: N/A
  • Average time to close pull requests: 2 months
  • Total issue authors: 0
  • Total pull request authors: 2
  • Average comments per issue: 0
  • Average comments per pull request: 1.43
  • Merged pull requests: 3
  • Bot issues: 0
  • Bot pull requests: 6
Past Year
  • Issues: 0
  • Pull requests: 0
  • Average time to close issues: N/A
  • Average time to close pull requests: N/A
  • Issue authors: 0
  • Pull request authors: 0
  • Average comments per issue: 0
  • Average comments per pull request: 0
  • Merged pull requests: 0
  • Bot issues: 0
  • Bot pull requests: 0
Top Authors
Issue Authors
Pull Request Authors
  • dependabot[bot] (6)
  • ckswls56 (1)
Top Labels
Issue Labels
Pull Request Labels
dependencies (6)

Packages

  • Total packages: 1
  • Total downloads:
    • pypi 212 last-month
  • Total dependent packages: 0
  • Total dependent repositories: 2
  • Total versions: 10
  • Total maintainers: 1
pypi.org: cache-simulator

A processor cache simulator for the MIPS ISA

  • Versions: 10
  • Dependent Packages: 0
  • Dependent Repositories: 2
  • Downloads: 212 Last month
Rankings
Forks count: 8.9%
Dependent packages count: 10.1%
Stargazers count: 11.0%
Average: 11.5%
Dependent repos count: 11.5%
Downloads: 15.8%
Maintainers (1)
Last synced: 7 months ago

Dependencies

requirements.txt pypi
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  • certifi ==2018.11.29
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  • flake8-polyfill ==1.0.2
  • idna ==2.8
  • isort ==4.3.4
  • mando ==0.6.4
  • mccabe ==0.6.1
  • nose ==1.3.7
  • packaging ==21.0
  • pkginfo ==1.5.0.1
  • pycodestyle ==2.4.0
  • pyflakes ==2.0.0
  • pyparsing ==2.4.7
  • radon ==2.2.0
  • readme-renderer ==24.0
  • rednose ==1.3.0
  • requests ==2.26.0
  • requests-toolbelt ==0.9.1
  • six ==1.10.0
  • termstyle ==0.1.11
  • testfixtures ==5.4.0
  • tqdm ==4.31.1
  • twine ==1.13.0
  • urllib3 ==1.26.6
  • webencodings ==0.5.1
.github/workflows/tests.yml actions
  • actions/checkout v3 composite
  • actions/setup-python v3 composite
  • coverallsapp/github-action master composite
pyproject.toml pypi
setup.py pypi