https://github.com/catarinaacsilva/md5-hardware
System based on hardware (FPGA) and software to implement MD5 Cryptographic Hash Function
Science Score: 10.0%
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○CITATION.cff file
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○codemeta.json file
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○.zenodo.json file
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○DOI references
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✓Academic publication links
Links to: sciencedirect.com -
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○JOSS paper metadata
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○Scientific vocabulary similarity
Low similarity (9.3%) to scientific vocabulary
Keywords
fpga
md5
performance
vitis
vivado
xilinx
Last synced: 5 months ago
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Repository
System based on hardware (FPGA) and software to implement MD5 Cryptographic Hash Function
Basic Info
- Host: GitHub
- Owner: catarinaacsilva
- License: mit
- Language: VHDL
- Default Branch: master
- Size: 286 MB
Statistics
- Stars: 2
- Watchers: 2
- Forks: 0
- Open Issues: 0
- Releases: 0
Topics
fpga
md5
performance
vitis
vivado
xilinx
Created almost 6 years ago
· Last pushed over 5 years ago
https://github.com/catarinaacsilva/md5-hardware/blob/master/
## MD5 Cryptographic Hash Function - Hardware and Software The main idea of this project is to implement a system where: - The most complexity part is implemented on hardware (MD5 hash function) - The interaction is implemented on software To explore the complexity and to compare two approaches: We developer a script to implement MD5 in C and compare the performance of three approaches: - All on software - All on hardware - MD5 on hardware and interaction on software The implementation will be based on this paper: [Hardware implementation of the MD5 algorithm](https://www.sciencedirect.com/science/article/pii/S1474667016324429). **Structure of the project:** - MD5Demo: Hardware + Software approach - hardware-md5: approach just on hardware - md5.c : script in C of MD5 - ip_repo: IP Core to Hardware + Software approach - simulation: testbench ## Requirements - Vivado 2019.2 - Vitis - Nexys4 Digilent Xilinx (FPGA) ## Implementation 1. On Vivado was implemented a version just on hardware with an IP Core to MD5. 2. Then, it was implemented a version with IP Core on hardware to implement MD5 and all the control on software. Input data came from software to hardware by DMA and all the process occurs on hardware. When the process finishes, the data produced on hardware is transmitted by AXI Memmory Mapped Interface to software to show the user.  3. Finish, the last version just on software was implemented (simple script). 4. It was counted the time on different approaches and compare results. ## Hardware + Software The IP Core to implement the MD5 function has a AXI Stream Slave interface and a AXI Memmory Mapped Interface. The follow images show the interaction:     On the AXI Stream Slave interface we have the following state machine:  ## Architecture  ## Authors * **Catarina Silva** - [catarinaacsilva](https://github.com/catarinaacsilva) ## License This project is licensed under the MIT License - see the [LICENSE](LICENSE) file for details
Owner
- Name: Catarina Silva
- Login: catarinaacsilva
- Kind: user
- Location: Portugal
- Company: IT Aveiro | UA
- Repositories: 3
- Profile: https://github.com/catarinaacsilva
Ph.D student | Computer science | MAP-i