https://github.com/coastalwhite/rvv-rust-stdarch
Generation script for the RISC-V Vector Intrinsics in Rust's stdarch
Science Score: 26.0%
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○CITATION.cff file
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○Scientific vocabulary similarity
Low similarity (3.8%) to scientific vocabulary
Last synced: 10 months ago
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Repository
Generation script for the RISC-V Vector Intrinsics in Rust's stdarch
Basic Info
- Host: GitHub
- Owner: coastalwhite
- Language: Python
- Default Branch: main
- Size: 7.81 KB
Statistics
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
- Releases: 0
Created over 2 years ago
· Last pushed over 2 years ago
Metadata Files
Readme
README.md
Generation script for RISC-V Vector Intrinsics in Rust
This repository contains a generation script to generate all the RISC-V Vector Intrinsics for the Scalable Vector RFC in Rust.
Usage
bash
./generate.py > rvv.rs
Status
- [ ] Memory Instructions
- [x] Unit-Stride
- [x] Unit-Stride Mask
- [x] Unit-Stride Fault-Only-First Loads
- [ ] Unit-Stride Segment
- [x] Constant-Stride
- [x] Constant-Stride Segment
- [x] Indexed Unordered
- [x] Indexed Ordered
- [x] Mask
- [ ] Indexed Unordered Segment
- [ ] Indexed Ordered Segment
- [ ] Whole Register
- [ ] Integer Arithmetic Instructions
- [x] Single-Width Add
- [x] Single-Width Subtract
- [ ] Single-Width Reverse Subtract
- [ ] Widening Add
- [ ] Signed
- [ ] Unsigned
- [ ] Widening Subtract
- [ ] Signed
- [ ] Unsigned
- [ ] Extension
- [ ] Add-with-Carry
- [ ] Subtract-with-Borrow
- [ ] Bitwise Logical
- [ ] And
- [ ] Or
- [ ] Xor
- [ ] Single-Width Shift
- [ ] Sll
- [ ] Srl
- [ ] Sra
- [ ] Narrowing Right Shift
- [ ] Srl
- [ ] Sra
- [ ] Compare
- [ ] Seq
- [ ] Sne
- [ ] Sltu
- [ ] Slt
- [ ] Sleu
- [ ] Sle
- [ ] Sgtu
- [ ] Sgt
- [ ] Min
- [ ] Signed
- [ ] Unsigned
- [ ] Max
- [ ] Signed
- [ ] Unsigned
- [ ] Single-Width Multiply
- [ ] Low
- [ ] Signed
- [ ] High
- [ ] Signed
- [ ] Unsigned
- [ ] Signed-Unsigned
- [ ] Divide
- [ ] Signed
- [ ] Unsigned
- [ ] Remainder
- [ ] Signed
- [ ] Unsigned
- [ ] Widening Multiply
- [ ] Signed
- [ ] Unsigned
- [ ] Signed-Unsigned
- [ ] Single-Width Multiply-Add
- [ ] Multiply-Add Overwrite AddEnd
- [ ] Multiply-Sub Overwrite MinUEnd
- [ ] Multiply-Add Overwrite Multiplicand
- [ ] Multiply-Sub Overwrite Multiplicand
- [ ] Widening Multiply-Add
- [ ] Unsigned Multiply-Add Overwrite AddEnd
- [ ] Signed Multiply-Add Overwrite AddEnd
- [ ] Signed-Unsigned Multiply-Add Overwrite AddEnd
- [ ] Unsigned-Signed Multiply-Add Overwrite AddEnd
- [ ] Merge
- [ ] Move
- [ ] Move
- [ ] Fixed-Point
- [ ] Single-Width Saturating Add
- [ ] Signed
- [ ] Unsigned
- [ ] Single-Width Saturating Subtract
- [ ] Signed
- [ ] Unsigned
- [ ] Single-Width Averaging Add
- [ ] Signed
- [ ] Unsigned
- [ ] Single-Width Averaging Subtract
- [ ] Signed
- [ ] Unsigned
- [ ] Single-Width Fractional Multiply with Rounding and Saturation
- [ ] Single-Width Scaling Shift
- [ ] Srl
- [ ] Sra
- [ ] Narrowing Fixed-Point Clip
- [ ] Signed
- [ ] Unsigned
- [ ] Floating-Point
- [ ] Single-Width Add
- [ ] Single-Width Subtract
- [ ] Single-Width Reverse Subtract
- [ ] Widening Add
- [ ] Widening Subtract
- [ ] Single-Width Multiply
- [ ] Single-Width Divide
- [ ] Single-Width Reverse Divide
- [ ] Widening Multiply
- [ ] Single-Width Fused Multiply-Add
- [ ] Multiply-Accumulate Overwrite Addend
- [ ] Negate-(Multiply-Accumulate) Overwrite Subtrahend
- [ ] Multiply-Subtract-Accumulator Overwrite Subtrahend
- [ ] Negate-(Multiply-Subtract-Accumulator) Overwrite Minuend
- [ ] Multiply-Add Overwrite Multiplicand
- [ ] Negate-(Multiply-Add) Overwrite Multiplicand
- [ ] Multiply-Sub Overwrite Multiplicand
- [ ] Negate-(Multiply-Sub) Overwrite Multiplicand
- [ ] Widening Fused Multiply-Add
- [ ] Multiply-Accumulate Overwrite Addend
- [ ] Negate-(Multiply-Accumulate) Overwrite Addend
- [ ] Multiply-Subtract-Accumulator Overwrite Addend
- [ ] Negate-(Multiply-Subtract-Accumulator) Overwrite Addend
- [ ] Square-Root
- [ ] Reciprocal Square-Root Estimate
- [ ] Reciprocal Estimate
- [ ] Min
- [ ] Max
- [ ] Sign-Injection
- [ ] Compare
- [ ] Eq
- [ ] Ne
- [ ] Lt
- [ ] Le
- [ ] Gt
- [ ] Ge
- [ ] Classify
- [ ] Merge
- [ ] Single-Width Integer Type-Convert
- [ ] Float to Unsigned Integer
- [ ] Float to Signed Integer
- [ ] Float to Unsigned Integer Truncating
- [ ] Float to Signed Integer Truncating
- [ ] Unsigned Integer to Float
- [ ] Signed Integer to Float
- [ ] Widening Integer Type-Convert
- [ ] Float to Double-Width Unsigned Integer
- [ ] Float to Double-Width Signed Integer
- [ ] Float to Double-Width Unsigned Integer Truncating
- [ ] Float to Double-Width Signed Integer Truncating
- [ ] Unsigned Integer to Double-Width Float
- [ ] Signed Integer to Double-Width Float
- [ ] Single-Width Float to Double-Width Float
- [ ] Narrowing Integer Type-Convert
- [ ] Double-Width Float to Unsigned Integer
- [ ] Double-Width Float to Signed Integer
- [ ] Double-Width Float to Unsigned Integer Truncating
- [ ] Double-Width Float to Signed Integer Truncating
- [ ] Double-Width Unsigned Integer to Float
- [ ] Double-Width Signed Integer to Float
- [ ] Double-Width Float to Single-Width Float
- [ ] Double-Width Float to Single-Width Float rounding towards odd
[ ] Reduction
- [ ] Single-Width Integer Reduction
- [ ] Sum
- [ ] Unsigned Max
- [ ] Signed Max
- [ ] Unsigned Min
- [ ] Signed Min
- [ ] And
- [ ] Or
- [ ] Xor
- [ ] Widening Integer Reduction
- [ ] Unsigned Sum
- [ ] Signed Sum
- [ ] Single-Width Floating-Point Reduction
- [ ] Ordered Sum
- [ ] Unordered Sum
- [ ] Min
- [ ] Max
- [ ] Widening Floating-Point Reduction
- [ ] Ordered Sum
- [ ] Unordered Sum
[ ] Mask
- [ ] Mask-Register Logical
- [ ] And
- [ ] Negate-And
- [ ] And-Negate
- [ ] Xor
- [ ] Or
- [ ] Nor
- [ ] Or-Negate
- [ ] Xnor
- [ ] Count Population
- [ ] Find-first-set bit
- [ ] Set-before-first bit
- [ ] Set-including-first bit
- [ ] Set-only-first bit
- [ ] Element Index
[ ] Permutation
- [ ] Integer Scalar Move
- [ ] Floating-Point Scalar Move
- [ ] Slide
- [ ] Slideup
- [ ] Slidedown
- [ ] Slide1up
- [ ] Slide1down
- [ ] Gather
- [ ] Compress
- [ ] Whole Register Move
Owner
- Name: Gijs Burghoorn
- Login: coastalwhite
- Kind: user
- Location: Netherlands
- Company: Polars
- Website: gburghoorn.com
- Repositories: 103
- Profile: https://github.com/coastalwhite
Rusty Hardware and Security Guy 🦀
GitHub Events
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Last synced: about 1 year ago
Top Committers
| Name | Commits | |
|---|---|---|
| Gijs Burghoorn | g****n@g****m | 4 |
Issues and Pull Requests
Last synced: about 1 year ago
All Time
- Total issues: 0
- Total pull requests: 0
- Average time to close issues: N/A
- Average time to close pull requests: N/A
- Total issue authors: 0
- Total pull request authors: 0
- Average comments per issue: 0
- Average comments per pull request: 0
- Merged pull requests: 0
- Bot issues: 0
- Bot pull requests: 0
Past Year
- Issues: 0
- Pull requests: 0
- Average time to close issues: N/A
- Average time to close pull requests: N/A
- Issue authors: 0
- Pull request authors: 0
- Average comments per issue: 0
- Average comments per pull request: 0
- Merged pull requests: 0
- Bot issues: 0
- Bot pull requests: 0