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Recent Releases of https://github.com/cornell-zhang/eqmap

https://github.com/cornell-zhang/eqmap - v0.8.0

What's Changed

  • Add purge function for ASIC tech mapping by @matth2k in https://github.com/cornell-zhang/eqmap/pull/154
  • Add missing input by @matth2k in https://github.com/cornell-zhang/eqmap/pull/155
  • Update crate name for paper by @matth2k in https://github.com/cornell-zhang/eqmap/pull/156
  • Driver tool renaming by @matth2k in https://github.com/cornell-zhang/eqmap/pull/157
  • Some docs polishing by @matth2k in https://github.com/cornell-zhang/eqmap/pull/158

Full Changelog: https://github.com/cornell-zhang/eqmap/compare/v0.7.2...v0.8.0

- Rust
Published by matth2k 11 months ago

https://github.com/cornell-zhang/eqmap - v0.7.2

What's Changed

  • Add basic report for ASIC by @matth2k in https://github.com/matth2k/lut-synth/pull/144
  • Add ASIC area model by @matth2k in https://github.com/matth2k/lut-synth/pull/145
  • Add total cell count to report by @matth2k in https://github.com/matth2k/lut-synth/pull/146
  • Refactor driver optimization strategies by @matth2k in https://github.com/matth2k/lut-synth/pull/147
  • Add CellLang to parse-verilog tool by @matth2k in https://github.com/matth2k/lut-synth/pull/149
  • Salvage SVModule with duplicate ports on emission by @matth2k in https://github.com/matth2k/lut-synth/pull/150
  • Fix optcell args and BUS cost by @matth2k in https://github.com/matth2k/lut-synth/pull/151
  • Check that circuit is fully mapped by default by @matth2k in https://github.com/matth2k/lut-synth/pull/152
  • Add equiv checking script for ASIC flow by @matth2k in https://github.com/matth2k/lut-synth/pull/153

Full Changelog: https://github.com/matth2k/lut-synth/compare/v0.7.1...v0.7.2

- Rust
Published by matth2k about 1 year ago

https://github.com/cornell-zhang/eqmap - v0.7.1

What's Changed

  • CellLang support multiple module outputs by @matth2k in https://github.com/matth2k/lut-synth/pull/140
  • Implement rest of PrimitiveTypes as rewrite rules by @matth2k in https://github.com/matth2k/lut-synth/pull/141
  • Implement most of the cells by @matth2k in https://github.com/matth2k/lut-synth/pull/142
  • Add rest of cells, refactor ASIC rewrites by @matth2k in https://github.com/matth2k/lut-synth/pull/143

Full Changelog: https://github.com/matth2k/lut-synth/compare/v0.7.0...v0.7.1

- Rust
Published by matth2k about 1 year ago

https://github.com/cornell-zhang/eqmap - v0.7.0

What's Changed

  • Adjust build params for cellmap by @matth2k in https://github.com/matth2k/lut-synth/pull/135
  • New setup for macOS by @arnavm30 in https://github.com/matth2k/lut-synth/pull/130
  • Move setup.zsh to correct directory by @matth2k in https://github.com/matth2k/lut-synth/pull/136
  • Finish Verilog backend unification by @matth2k in https://github.com/matth2k/lut-synth/pull/137
  • Refactor frontend Verilog compilation by @matth2k in https://github.com/matth2k/lut-synth/pull/138
  • Add top-level ASIC tool by @matth2k in https://github.com/matth2k/lut-synth/pull/139

Full Changelog: https://github.com/matth2k/lut-synth/compare/v0.6.3...v0.7.0

- Rust
Published by matth2k about 1 year ago

https://github.com/cornell-zhang/eqmap - v0.6.3

What's Changed

  • Add LUT1 to simlib by @matth2k in https://github.com/matth2k/lut-synth/pull/125
  • Fix node definitions in e-graph dumps by @matth2k in https://github.com/matth2k/lut-synth/pull/126
  • Update serialized node names for SmoothE by @matth2k in https://github.com/matth2k/lut-synth/pull/127
  • Generate more concise proofs by @matth2k in https://github.com/matth2k/lut-synth/pull/128
  • Revise README by @matth2k in https://github.com/matth2k/lut-synth/pull/129
  • Refactor driver in terms of new CircuitLang trait by @matth2k in https://github.com/matth2k/lut-synth/pull/131
  • Initial commit of ASIC tech mapping by @matth2k in https://github.com/matth2k/lut-synth/pull/132
  • Verilog emission refactor by @matth2k in https://github.com/matth2k/lut-synth/pull/133
  • Bump version by @matth2k in https://github.com/matth2k/lut-synth/pull/134

Full Changelog: https://github.com/matth2k/lut-synth/compare/v0.6.2...v0.6.3

- Rust
Published by matth2k about 1 year ago

https://github.com/cornell-zhang/eqmap - v0.6.2

What's Changed

  • Add graph_dumps feature by @matth2k in https://github.com/matth2k/lut-synth/pull/123
  • Fix setup script for when build fails by @matth2k in https://github.com/matth2k/lut-synth/pull/124

Full Changelog: https://github.com/matth2k/lut-synth/compare/v0.6.1...v0.6.2

- Rust
Published by matth2k about 1 year ago

https://github.com/cornell-zhang/eqmap - v0.6.1

What's Changed

  • Refactor runner limits into a BuildStrat by @matth2k in https://github.com/matth2k/lut-synth/pull/118
  • Add time progress bar by @matth2k in https://github.com/matth2k/lut-synth/pull/119
  • Fix wire decl for escaped names by @matth2k in https://github.com/matth2k/lut-synth/pull/120
  • Let CTRL+C interrupt e-graph build by @matth2k in https://github.com/matth2k/lut-synth/pull/121
  • Change how nets are named by @matth2k in https://github.com/matth2k/lut-synth/pull/122

Full Changelog: https://github.com/matth2k/lut-synth/compare/v0.6.0...v0.6.1

- Rust
Published by matth2k about 1 year ago

https://github.com/cornell-zhang/eqmap - v0.6.0 Rust 2024 Edition

- Rust
Published by matth2k about 1 year ago

https://github.com/cornell-zhang/eqmap - v0.5.3

What's Changed

  • Don't use SRL with Yosys by @matth2k in https://github.com/matth2k/lut-synth/pull/113
  • Fix calculating input size in reports by @matth2k in https://github.com/matth2k/lut-synth/pull/114
  • Add --reg-weight flag by @matth2k in https://github.com/matth2k/lut-synth/pull/115

Full Changelog: https://github.com/matth2k/lut-synth/compare/v0.5.2...v0.5.3

- Rust
Published by matth2k about 1 year ago

https://github.com/cornell-zhang/eqmap - v0.5.2 Bug Fixes

What's Changed

  • Add VCC primitive by @matth2k in https://github.com/matth2k/lut-synth/pull/110
  • Full support for don't care values by @matth2k in https://github.com/matth2k/lut-synth/pull/111
  • Update verify() for misplaced integers by @matth2k in https://github.com/matth2k/lut-synth/pull/112

Full Changelog: https://github.com/matth2k/lut-synth/compare/v0.5.1...v0.5.2

- Rust
Published by matth2k over 1 year ago

https://github.com/cornell-zhang/eqmap - v0.5.1 Bug Fixes

What's Changed

  • Add parameter for decompose in any order by @matth2k in https://github.com/matth2k/lut-synth/pull/100
  • Add append.py script by @matth2k in https://github.com/matth2k/lut-synth/pull/101
  • Support GND primitive by @matth2k in https://github.com/matth2k/lut-synth/pull/102
  • Support Verilog instances with constant inputs by @arnavm30 in https://github.com/matth2k/lut-synth/pull/103
  • Propagate literal parsing errors by @matth2k in https://github.com/matth2k/lut-synth/pull/104
  • Allow 'Don't Care' to be parsed into LutLang by @matth2k in https://github.com/matth2k/lut-synth/pull/105
  • Speed up cycle detection by @matth2k in https://github.com/matth2k/lut-synth/pull/108
  • Bump version by @matth2k in https://github.com/matth2k/lut-synth/pull/109

Full Changelog: https://github.com/matth2k/lut-synth/compare/v0.5.0...v0.5.1

- Rust
Published by matth2k over 1 year ago

https://github.com/cornell-zhang/eqmap - v0.5.0

What's Changed

  • Add disassemble extraction strategy by @matth2k in https://github.com/matth2k/lut-synth/pull/83
  • Add disassembly test by @matth2k in https://github.com/matth2k/lut-synth/pull/84
  • Add --verbose option to parse-verilog by @matth2k in https://github.com/matth2k/lut-synth/pull/86
  • Fix outputs driven directly by an input by @matth2k in https://github.com/matth2k/lut-synth/pull/87
  • Don't add outputs directly to signals list by @matth2k in https://github.com/matth2k/lut-synth/pull/89
  • Fix Verilog when multiple outputs assign to the same net by @matth2k in https://github.com/matth2k/lut-synth/pull/90
  • Add reconfigurable disassemble extraction strategy by @matth2k in https://github.com/matth2k/lut-synth/pull/91
  • Don't need to clone the SynthRequest by @matth2k in https://github.com/matth2k/lut-synth/pull/93
  • Follow Verilog rule for escape identifiers by @matth2k in https://github.com/matth2k/lut-synth/pull/94
  • Remove command option for fam, update docs by @matth2k in https://github.com/matth2k/lut-synth/pull/95
  • Added lvv-vivado by @berkgokmen14 in https://github.com/matth2k/lut-synth/pull/96
  • Support MUXF7 by @matth2k in https://github.com/matth2k/lut-synth/pull/97
  • Move mux expansion rule by @matth2k in https://github.com/matth2k/lut-synth/pull/98
  • Add driver script for re-synthesis feature by @matth2k in https://github.com/matth2k/lut-synth/pull/99

Full Changelog: https://github.com/matth2k/lut-synth/compare/v0.3.2...v0.5.0

- Rust
Published by matth2k over 1 year ago

https://github.com/cornell-zhang/eqmap - v0.3.2

What's Changed

  • Add gate info to report by @matth2k in https://github.com/matth2k/lut-synth/pull/80
  • Track cut information in analysis by @matth2k in https://github.com/matth2k/lut-synth/pull/77
  • Implement dynamic decompositions by @matth2k in https://github.com/matth2k/lut-synth/pull/82

Full Changelog: https://github.com/matth2k/lut-synth/compare/v0.3.0...v0.3.2

- Rust
Published by matth2k over 1 year ago

https://github.com/cornell-zhang/eqmap - v0.3.0

Included are x86 gnu linux binaries.

What's Changed

  • Handle arbitrary assignments in Verilog by @matth2k in https://github.com/matth2k/lut-synth/pull/62
  • Add register count to report by @matth2k in https://github.com/matth2k/lut-synth/pull/63
  • fix shebangs by @arnavm30 in https://github.com/matth2k/lut-synth/pull/65
  • Add cat.py to tool path by @matth2k in https://github.com/matth2k/lut-synth/pull/66
  • Add stop reason to report by @matth2k in https://github.com/matth2k/lut-synth/pull/68
  • Add ILP extractor by @matth2k in https://github.com/matth2k/lut-synth/pull/70
  • Fix file perms by @matth2k in https://github.com/matth2k/lut-synth/pull/71
  • Save version information with flag by @matth2k in https://github.com/matth2k/lut-synth/pull/72
  • Parse escaped identifiers in verilog by @berkgokmen14 in https://github.com/matth2k/lut-synth/pull/73
  • Add CYCLE and ARG node types by @berkgokmen14 in https://github.com/matth2k/lut-synth/pull/76
  • Assign Verilog outputs in correct order by @matth2k in https://github.com/matth2k/lut-synth/pull/78
  • Bump version to 0.3 by @matth2k in https://github.com/matth2k/lut-synth/pull/79

New Contributors

  • @arnavm30 made their first contribution in https://github.com/matth2k/lut-synth/pull/65

Full Changelog: https://github.com/matth2k/lut-synth/compare/v0.2.0...v0.3.0

- Rust
Published by matth2k over 1 year ago

https://github.com/cornell-zhang/eqmap - v0.2.0

Here is some initial results on compiling the MCNC benchmarks from https://github.com/lsils/SCE-benchmarks/tree/main/MCNC/original

The binaries were built on Ubuntu 24.04.1 LTS

- Rust
Published by matth2k over 1 year ago