ethernet-packet-generator-hardware-prototype
A basic ethernet packet generator hardware prototype description in Verilog-HDL
https://github.com/nettimi-satya-sai-srinivas/ethernet-packet-generator-hardware-prototype
Science Score: 44.0%
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✓CITATION.cff file
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○Scientific vocabulary similarity
Low similarity (5.3%) to scientific vocabulary
Repository
A basic ethernet packet generator hardware prototype description in Verilog-HDL
Basic Info
- Host: GitHub
- Owner: Nettimi-Satya-Sai-Srinivas
- License: gpl-3.0
- Language: Verilog
- Default Branch: main
- Size: 81.1 KB
Statistics
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
- Releases: 0
Metadata Files
README.md
ethernet-packet-generator-hardware-prototype
A basic ethernet packet generator hardware prototype description in Verilog-HDL
The objective of this project is to develop a custom hardware for a basic ethernet packet generator. Special emphasis is given only on the packet generation process and the pre-requisites for packet genertaion are assumed to be well known in advance.
This project comprises: - a ethernet packet generator, i.e., epg.v, design source - a testbench source, i.e., design1wrapper_tb.v
A block design environment has been created, wherein the epg module is included along with few inbuit Xilinx IPs namely, FIFO generator and utility vector logic, as illustrated in the Block Design.pdf file. A top hdl wrapper has been generated for the block design, and simulated using design1wrapper_tb.v testbench.
The FIFO is configured to prestore the data required for frame generation.
To know about the ethernet frame structure, kindly refer the following youtube video:
https://www.youtube.com/watch?v=2qvwuxuZPN8
Owner
- Name: Nettimi Satya Sai Srinivas
- Login: Nettimi-Satya-Sai-Srinivas
- Kind: user
- Location: Karaikal, Union Territory of Puducherry, India
- Company: National Institute of Technology Puducherry Karaikal
- Website: https://sites.google.com/site/nssaisrinivas/
- Twitter: NettimiSrinivas
- Repositories: 1
- Profile: https://github.com/Nettimi-Satya-Sai-Srinivas
I am Research Associate, in the Department of Electronics and Communication Engineering, at National Institute of Technology Puducherry, Karaikal, India.
Citation (CITATION.cff)
cff-version: 1.2.0 message: "If you use this software, please cite it as below." authors: - family-names: "Nettimi" given-names: "Satya Sai Srinivas" orcid: "https://orcid.org/0000-0002-1877-2434" title: "ethernet-packet-generator-hardware-prototype" version: 1.0.0 doi: 10.5281/zenodo.1234 date-released: 2021-12-28 url: "https://github.com/Nettimi-Satya-Sai-Srinivas/ethernet-packet-generator-hardware-prototype"