rfsoc_dds

Systemverilog for direct digital synthesis of high-purity sinusoids for use with RFSoCs running at full sample rate

https://github.com/qnngroup/rfsoc_dds

Science Score: 26.0%

This score indicates how likely this project is to be science-related based on various indicators:

  • CITATION.cff file
  • codemeta.json file
    Found codemeta.json file
  • .zenodo.json file
    Found .zenodo.json file
  • DOI references
  • Academic publication links
  • Academic email domains
  • Institutional organization owner
  • JOSS paper metadata
  • Scientific vocabulary similarity
    Low similarity (7.0%) to scientific vocabulary

Keywords

direct-digital-synthesis rfsoc systemverilog
Last synced: 10 months ago · JSON representation

Repository

Systemverilog for direct digital synthesis of high-purity sinusoids for use with RFSoCs running at full sample rate

Basic Info
  • Host: GitHub
  • Owner: qnngroup
  • License: mit
  • Language: Jupyter Notebook
  • Default Branch: main
  • Homepage:
  • Size: 31.3 MB
Statistics
  • Stars: 0
  • Watchers: 1
  • Forks: 0
  • Open Issues: 0
  • Releases: 2
Topics
direct-digital-synthesis rfsoc systemverilog
Created about 3 years ago · Last pushed over 2 years ago
Metadata Files
Readme License Citation

README.md

rfsoc_dds

Systemverilog for direct digital synthesis of high-purity sinusoids at full sample rate for use with RFSoCs. Also includes a sample buffer that can perform basic amplitude discrimination on input signals to generate sparse sequences of samples that are time-tagged.

Repo structure

dds_test.srcs:

Systemverilog for simulation and synthesis. The key module for direct digital synthesis (DDS) is here. DDS is implemented multiple phase increment registers configured in parallel. A four-quadrant lookup table is used (I didn't have the energy to optimize a single quadrant scheme to minimize phase quantization noise for only 4x improvement in storage space). To reduce phase quantization noise, a maximal linear-feedback shift register (LFSR) is used to provide a 1-LSB dither signal. While this increases the floor of the phase noise as compared to a 0.5-LSB dither, I found in testing that it reduced the correlated phase noise and improved the spurious-free dynamic range of the output.

Owner

  • Name: QNN Group
  • Login: qnngroup
  • Kind: organization
  • Location: Massachusetts Institute of Technology

Quantum Nanostructures & Nanofabrication group at Massachusetts Institute of Technology

GitHub Events

Total
Last Year