cvfpu - v0.8.1

Create release 0.8.1:

• Fix Underflow flag for MUL and DIV/SQRT operations (#94 #726 #729)
• Fix for Float to Int conversion (#97 #83 #727)
• Fixed unnecessary trailing semicolon (#99)

- SystemVerilog
Published by pascalgouedo over 2 years ago

cvfpu - v0.8.0

Create release 0.8.0:

• Add external reg enable to slices (#89)
• Integrate new 32b divider (#79)
• Moved @lucabertaccini to Authors
• Added Pasquale Davide Schiavone and Pascal Gouedo as maintainers
• multifmt slice uses wrong FP width for third operand (#86)
• Fix DivSqrt lanes synchronization (#90)

- SystemVerilog
Published by davideschiavone over 2 years ago

cvfpu - v0.7.0

Create release 0.7.0:

• Align CVFPU to RVV requirements (ARA branch merged)
• Fix f2i cast edge cases
• Fix RDN bug in floating-point multiplications
• Fix shift amount width in fma and fma_multi

- SystemVerilog
Published by lucabertaccini almost 3 years ago

cvfpu - v0.6.6

Changed

• ⬆️ [common_cells] Bump common cells version (#44)

- SystemVerilog
Published by stmach almost 5 years ago

cvfpu - v0.6.4

Fixed

• 🔧 Updated dependencies for Bender and IPApproX (#37)
• ⬆️ [fpudivsqrt_mvp] Bump for formal version number

- SystemVerilog
Published by stmach over 5 years ago

cvfpu - v0.6.3

Fixed

• 👕 Fix undriven signals for inactive case in fpnew_fma_multi
• 👕 Fix potentially uncovered case item in fpnew_pkg
• 👕 Undriven unused portions of signals in multi-format slices
• 👕 Undriven portions of the result for non-divisible unit width & format width in multi-format slices
• ⬆️ [fpudivsqrt_mvp] Bumped to fix signalling for underflows

- SystemVerilog
Published by stmach over 5 years ago

cvfpu - v0.6.2

Changed

• 🐛 Number of pipeline registers in multi-format units is the maximum of all contained formats instead of the first format marked MERGED

Fixed

• 📚 Typo in changelog
• 🐛 Missing type cast breaking simulation in VCS (#24)

- SystemVerilog
Published by stmach over 5 years ago

cvfpu - v0.6.1

Fixed

• 🐛 A bug where the div/sqrt unit could lose operations in flight

- SystemVerilog
Published by stmach over 6 years ago

cvfpu - v0.6.0

New in 0.6.0

Changed

• ♻️ Pipelines are generated in the datapath modules instead of separate instances

Fixed

• 👾 Don't care assignments to structs have been expanded for better tool support (#14)
• 🐛 Undriven busy signal in output pipeline bypass
• 📚 Typo in the documentation about the multiply operation
• 🐛 Generation of merged slices when the first package format is disabled
• 👾 Potential simulation/synthesis mismatch of the UF flag
• 👕 Various linter warnings
• 📚 Documentation to reflect on updated pipeline distribution order
• ⬆️ [fpudivsqrt_mvp] Bumped to fix linter warnings
• 🔧 [Bender] Fixed dependencies for Bender (#15)

Removed

• 🔥 Currently unused modules: fpnew_pipe*, fpnew_{f2i,f2f,i2f}_cast

Other changes since 0.5.0

Added

• 📚 Documentation about multi-format operations
• 📚 Extended pipelining description slightly
• 📚 Extended semantic versioning declaration in changelog

Changed

• ✨ Don't care logic value can be changed from the package now
• 🐎 Default pipeline config in the package is now BEFORE
• 📚 Updated diagrams in architecture documentation

Fixed

• 👾 Don't care values are assigned '1 instead of 'X by default
• 🐛 UF flag handling according to IEEE754-2008 (#11)
• 🔧 ipslist.yml entry for updated commoncells
• 🐛 Internal pipeline bypass in cast unit
• 🔧 Include path for common_cells in src_files.yml
• ⬆️ [commoncells] Bumped to fix srcfiles.yml bugs
• ⬆️ [fpudivsqrt_mvp] Bumped to fix linter warnings

- SystemVerilog
Published by stmach over 6 years ago

cvfpu - v0.5.6

Changed

• :sparkles: Don't care logic value can be changed from the package now
• 🐎 Default pipeline config in the package is now BEFORE

Fixed

• 👾 Don't care values are assigned '1 instead of 'X by default

- SystemVerilog
Published by stmach over 6 years ago

cvfpu - v0.5.5

Fixed

• :bug: UF flag handling according to IEEE754-2008 (#11)

- SystemVerilog
Published by stmach over 6 years ago

cvfpu - v0.5.4

Added

• :books: Documentation about multi-format operations
• :books: Extended pipelining description slightly
• :books: Extended semantic versioning declaration in changelog

Changed

• :books: Updated diagrams in architecture documentation

Fixed

• ⬆️ [commoncells] Bumped to fix srcfiles.yml bugs
• ⬆️ [fpudivsqrt_mvp] Bumped to fix linter warnings

- SystemVerilog
Published by stmach over 6 years ago

cvfpu - v0.5.3

Fixed

• 🔧 ipslist.yml entry for updated commoncells

- SystemVerilog
Published by stmach almost 7 years ago

cvfpu - v0.5.2

Fixed

• :bug: Internal pipeline bypass in cast unit

- SystemVerilog
Published by stmach almost 7 years ago

cvfpu - v0.5.1

Fixed

• 🔧 Include path for common_cells in src_files.yml

- SystemVerilog
Published by stmach almost 7 years ago

cvfpu - v0.5.0

First versioned release

Added

• ✨ The FPU :)
• :books: Initial Documentation

Changed

• :books: "Restarted" the changelog as the old one was stale

Fixed

• :bug: Handling of exception flags for infinity operands

- SystemVerilog
Published by stmach almost 7 years ago