Releases | Open Source Science

What's Changed

[rtl] derive all memories from generic RAM primitives by @stnolting in https://github.com/stnolting/neorv32/pull/1347
[rtl] add all-new FIFO primitive by @stnolting in https://github.com/stnolting/neorv32/pull/1349
[demo_semihosting] use 4-byte instead of 16-byte alignment by @vogma in https://github.com/stnolting/neorv32/pull/1350
🐛 fix simulation memory-component by @stnolting in https://github.com/stnolting/neorv32/pull/1352
⚠️ simplify SLINK, SPI and NEOLED modules by @stnolting in https://github.com/stnolting/neorv32/pull/1353
⚠️ simplify UART and SDI modules by @stnolting in https://github.com/stnolting/neorv32/pull/1354
simplify ROM images (VHDL packages for IMEM/BOOTROM) by @stnolting in https://github.com/stnolting/neorv32/pull/1355
[rtl] minor code-cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/1357
[sdi] add RX & TX FIFO clear flags by @stnolting in https://github.com/stnolting/neorv32/pull/1358
⚠️ rework TWD module by @stnolting in https://github.com/stnolting/neorv32/pull/1359
fix minor RISC-V incompatibilities by @stnolting in https://github.com/stnolting/neorv32/pull/1360

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.12.0...v1.12.1

- VHDL
Published by stnolting 6 months ago

What's Changed

⚠️ [CPU] remove double-trap exception by @stnolting in https://github.com/stnolting/neorv32/pull/1332
minor fixes and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/1333
Add NEORV32-specifc "machine control and status" CSR (mxcsr) by @stnolting in https://github.com/stnolting/neorv32/pull/1335
Add new tuning option: Constant-time branches by @stnolting in https://github.com/stnolting/neorv32/pull/1338
Rework bus access error logic by @stnolting in https://github.com/stnolting/neorv32/pull/1339
⚠️ [SYSINFO] rework layout of "MISC" information register by @stnolting in https://github.com/stnolting/neorv32/pull/1342
[rtl] replace individual IMEM & DMEM modules by a generic memory component by @stnolting in https://github.com/stnolting/neorv32/pull/1344
[Vivado IP] Remove relative paths from the IP-packaging script by @stnolting in https://github.com/stnolting/neorv32/pull/1341
rtl code cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/1345
🐛 [dma] fix byte-enable signal for byte-reads by @stnolting in https://github.com/stnolting/neorv32/pull/1346

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.11.9...v1.12.0

- VHDL
Published by stnolting 6 months ago

What's Changed

🐛 fix double-trap tracking bug by @stnolting in https://github.com/stnolting/neorv32/pull/1312
✨ add new module: execution trace buffer (TRACER) by @stnolting in https://github.com/stnolting/neorv32/pull/1313
Cleanup UART simulation logging by @stnolting in https://github.com/stnolting/neorv32/pull/1314
Replace trace with trace_s in the top by @Unike267 in https://github.com/stnolting/neorv32/pull/1316
Add GDB tracer support by @stnolting in https://github.com/stnolting/neorv32/pull/1317
[tracer] write full trace log to file by @stnolting in https://github.com/stnolting/neorv32/pull/1318
:sparkles: add support for RISC-V Zcb ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/1320
extend tracer simulation log; improve semihosting by @stnolting in https://github.com/stnolting/neorv32/pull/1322
Make cache/AXI bursts optional by @stnolting in https://github.com/stnolting/neorv32/pull/1324
Minor rtl edits and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/1325
minor rtl edits and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/1331

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.11.8...v1.11.9

- VHDL
Published by stnolting 7 months ago

New Features

add double-trap exception (loosely based on the RISC-V Smdbltrp ISA extension)
add support for hardware-assisted watchpoints (on-chip debugger)
add configurable number of hardware break-/watchpoint (0..16)

What's Changed

remove WDT "strict" bit; minor code edits and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/1293
🧪 add double-trap exception by @stnolting in https://github.com/stnolting/neorv32/pull/1294
Rework RTE trap handler look-up-table by @stnolting in https://github.com/stnolting/neorv32/pull/1295
[rte] cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/1299
minor rtl edits and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/1302
Feature: Libero support by @hughbreslin in https://github.com/stnolting/neorv32/pull/1300
[ocd] add support for hardware watchpoints by @stnolting in https://github.com/stnolting/neorv32/pull/1303
✨ add configurable number of break-/watchpoints by @stnolting in https://github.com/stnolting/neorv32/pull/1304
minor rtl edits and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/1307
⚠️ [top] remove HART_BASE generic by @stnolting in https://github.com/stnolting/neorv32/pull/1308
[cache] fix minimal cache block size by @stnolting in https://github.com/stnolting/neorv32/pull/1310

New Contributors

@hughbreslin made their first contribution in https://github.com/stnolting/neorv32/pull/1300

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.11.7...v1.11.8

- VHDL
Published by stnolting 8 months ago

What's Changed

[cpu] Minor rtl optimizations and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/1283
upgrade TRNG to neoTRNG v3.3 by @stnolting in https://github.com/stnolting/neorv32/pull/1284
✨ on chip debugger: add semihosting support by @stnolting in https://github.com/stnolting/neorv32/pull/1285
:warning: combine SLINK's RX and TX interrupts into a single interrupt by @stnolting in https://github.com/stnolting/neorv32/pull/1286
✨ add TRNG interrupt by @stnolting in https://github.com/stnolting/neorv32/pull/1287
⚠️ rework UART "TX FIFO full" status flag by @stnolting in https://github.com/stnolting/neorv32/pull/1288
⚠️ combine UART's RX and TX interrupts into a single interrupt by @stnolting in https://github.com/stnolting/neorv32/pull/1289
Minor rtl edits and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/1291
Remove enable logic for SoC-wide clock generator by @stnolting in https://github.com/stnolting/neorv32/pull/1292

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.11.6...v1.11.7

- VHDL
Published by stnolting 8 months ago

What's Changed

:bug: fix byte-enable bus signal for instruction fetch accesses by @stnolting in https://github.com/stnolting/neorv32/pull/1272
minor rtl edits and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/1273
⚠️ CFS IO rework by @stnolting in https://github.com/stnolting/neorv32/pull/1274
⚠️ remove CRC module by @stnolting in https://github.com/stnolting/neorv32/pull/1275
Rework IMEM & DMEM RAM style by @stnolting in https://github.com/stnolting/neorv32/pull/1277
[cpu] rework instruction trap logic by @stnolting in https://github.com/stnolting/neorv32/pull/1278
🧪 rework DMA controller by @stnolting in https://github.com/stnolting/neorv32/pull/1279
⚠️ Rename IMEM/DMEM configuration generics by @stnolting in https://github.com/stnolting/neorv32/pull/1280
Add optional IMEM/DMEM output register stages by @stnolting in https://github.com/stnolting/neorv32/pull/1281

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.11.5...v1.11.6

- VHDL
Published by stnolting 9 months ago

What's Changed

Rework caches; use "write-through" strategy by @stnolting in https://github.com/stnolting/neorv32/pull/1259
Rework locking of processor-internal bus by @stnolting in https://github.com/stnolting/neorv32/pull/1260
minor edits and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/1262
✨ add cache burst transfers by @stnolting in https://github.com/stnolting/neorv32/pull/1263
[bus] add explicit burst signal to internal processor bus by @stnolting in https://github.com/stnolting/neorv32/pull/1265
🐛 Fix missing burst signal in bus register stage by @stnolting in https://github.com/stnolting/neorv32/pull/1266
⚠️ make MCAUSE CSR read-only by @stnolting in https://github.com/stnolting/neorv32/pull/1267
⚠️ [inter-processor communication] remove hardware spinlocks and inter-core communication links by @stnolting in https://github.com/stnolting/neorv32/pull/1268
:bug: fix CPU bus issues by @stnolting in https://github.com/stnolting/neorv32/pull/1270

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.11.4...v1.11.5

- VHDL
Published by stnolting 9 months ago

What's Changed

Make hardware breakpoint optional; constrain to debug-mode only by @stnolting in https://github.com/stnolting/neorv32/pull/1239
🐛 [bootloader] fix privilege at application start by @stnolting in https://github.com/stnolting/neorv32/pull/1241
Optimize round-robin bus switch: remove idle cycles by @stnolting in https://github.com/stnolting/neorv32/pull/1244
Add bus lock feature by @stnolting in https://github.com/stnolting/neorv32/pull/1245
Optimize cache system by @stnolting in https://github.com/stnolting/neorv32/pull/1248
Rework newlib system calls by @stnolting in https://github.com/stnolting/neorv32/pull/1249
⚠️ Rework processor-internal bus protocol by @stnolting in https://github.com/stnolting/neorv32/pull/1252
Add full-scale AXI4 bridge by @stnolting in https://github.com/stnolting/neorv32/pull/1253
[docs] fix dead link to setups by @josuah in https://github.com/stnolting/neorv32/pull/1255
⚠️ Remove external bus interface cache (xbus-cache) by @stnolting in https://github.com/stnolting/neorv32/pull/1256
:warning: Rework cache configuration options by @stnolting in https://github.com/stnolting/neorv32/pull/1257

New Contributors

@josuah made their first contribution in https://github.com/stnolting/neorv32/pull/1255

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.11.3...v1.11.4

- VHDL
Published by stnolting 10 months ago

What's Changed

[docs] inline Wavedrom scripts by @stnolting in https://github.com/stnolting/neorv32/pull/1208
docs: datasheet: cpu: fix name for the "A" ISA extension by @henrikbrixandersen in https://github.com/stnolting/neorv32/pull/1209
build: rebuild exe when header files change by @ecstrema in https://github.com/stnolting/neorv32/pull/1212
fix litex boot by @pepijndevos in https://github.com/stnolting/neorv32/pull/1211
⚠️ Remove CPU clock gating option by @stnolting in https://github.com/stnolting/neorv32/pull/1214
[rtl/sw] Add twd dummy byte, add twd bootloader and smaller fixes by @LukasP46 in https://github.com/stnolting/neorv32/pull/1210
✨ Add 32 hardware spinlocks by @stnolting in https://github.com/stnolting/neorv32/pull/1220
:bug: fix PWM prescaler by @stnolting in https://github.com/stnolting/neorv32/pull/1222
🐛 [linker] fix alignment of init/fini arrays by @stnolting in https://github.com/stnolting/neorv32/pull/1224
Minor rtl edits and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/1225
[sw/lib] add restart/reset functions by @stnolting in https://github.com/stnolting/neorv32/pull/1226
:bug: [SDI] fix input synchronizer by @stnolting in https://github.com/stnolting/neorv32/pull/1227
[sw/lib/neoled] fix neoled "irqmode" not a applied in "neorv32neoled_setup" and [sw/lib/neoled] updated doxygen comments by @SirBramble in https://github.com/stnolting/neorv32/pull/1228
Add support for setting PWM polarity by @henrikbrixandersen in https://github.com/stnolting/neorv32/pull/1230
[sw] cleanup main software makefile, add git tag, add verbosity configuration by @stnolting in https://github.com/stnolting/neorv32/pull/1231
[sw/bootloader] TWI fix for bootloader by @SirBramble in https://github.com/stnolting/neorv32/pull/1229
Rework bootloader by @stnolting in https://github.com/stnolting/neorv32/pull/1215
[rtl/pmp] fix multiple signal assignment by @NikLeberg in https://github.com/stnolting/neorv32/pull/1236
[rtl/core/twi] delay sda low by @SirBramble in https://github.com/stnolting/neorv32/pull/1237

New Contributors

@SirBramble made their first contribution in https://github.com/stnolting/neorv32/pull/1228

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.11.2...v1.11.3

- VHDL
Published by stnolting 10 months ago

What's Changed

✨ add support for Zalrsc ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/1181
Minor rtl optimizations and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/1182
Source-out CPU front-end by @stnolting in https://github.com/stnolting/neorv32/pull/1183
⚠️ Software libraries cleanup by @stnolting in https://github.com/stnolting/neorv32/pull/1186
Fix Bootloader Makefile UART_BAUD by @lebruu in https://github.com/stnolting/neorv32/pull/1189
🐛 fix bug in Zalrsc ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/1190
[rtl] minor edits and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/1191
[cpu] relocate CPU counters by @stnolting in https://github.com/stnolting/neorv32/pull/1192
minor rtl edits by @stnolting in https://github.com/stnolting/neorv32/pull/1193
⚠️ rework DMA and GPTMR by @stnolting in https://github.com/stnolting/neorv32/pull/1194
rtl: processor_templates: enable Zicntr ISA extension on minimal templates by @henrikbrixandersen in https://github.com/stnolting/neorv32/pull/1196
Fix: quote readlink to fix windows make check by @ecstrema in https://github.com/stnolting/neorv32/pull/1197
fix: increment location counter with heap size by @brkydnc in https://github.com/stnolting/neorv32/pull/1201
Add NUMA LiteX configuration by @pepijndevos in https://github.com/stnolting/neorv32/pull/1204
:bug: Fix Zbb shift instructions by @stnolting in https://github.com/stnolting/neorv32/pull/1206
:warning: rename SPI & TWI transfer functions by @stnolting in https://github.com/stnolting/neorv32/pull/1207

New Contributors

@lebruu made their first contribution in https://github.com/stnolting/neorv32/pull/1189
@ecstrema made their first contribution in https://github.com/stnolting/neorv32/pull/1197
@brkydnc made their first contribution in https://github.com/stnolting/neorv32/pull/1201
@pepijndevos made their first contribution in https://github.com/stnolting/neorv32/pull/1204

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.11.1...v1.11.2

- VHDL
Published by stnolting 11 months ago

What's Changed

[rtl] reset SDA and SCL of TWI and TWD to '1' by @LukasP46 in https://github.com/stnolting/neorv32/pull/1167
⚠️ rename JEDEC ID generic; minor rtl edits and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/1168
🐛 fix BOOTROM addressing by @stnolting in https://github.com/stnolting/neorv32/pull/1171
🐛 Fix crt0's main entry address being overridden by constructors by @stnolting in https://github.com/stnolting/neorv32/pull/1172
Minor rtl optimizations and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/1174
⚠️ remove execute in-place (XIP) module by @stnolting in https://github.com/stnolting/neorv32/pull/1175
[cfs] Add missing CFS clock gen enable signal. by @Sazzach in https://github.com/stnolting/neorv32/pull/1177
✨ add memory coherency logic by @stnolting in https://github.com/stnolting/neorv32/pull/1176
Doc ds fixes by @DAR0001 in https://github.com/stnolting/neorv32/pull/1178
[docs] SPI: minor fixes by @stnolting in https://github.com/stnolting/neorv32/pull/1166
Minor rtl edits and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/1179
:warning: rename UART RTS/CTS signals by @stnolting in https://github.com/stnolting/neorv32/pull/1180

New Contributors

@Sazzach made their first contribution in https://github.com/stnolting/neorv32/pull/1177
@DAR0001 made their first contribution in https://github.com/stnolting/neorv32/pull/1178

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.11.0...v1.11.1

- VHDL
Published by stnolting about 1 year ago

What's Changed

fix CSR read operations (side effects) by @stnolting in https://github.com/stnolting/neorv32/pull/1145
[sw/bootloader] add TWI boot option by @LukasP46 in https://github.com/stnolting/neorv32/pull/1108
SMP dual-core cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/1146
[control] separate fence and fence.i instructions by @stnolting in https://github.com/stnolting/neorv32/pull/1149
⚠️ [rte] use a single, global trap handler table by @stnolting in https://github.com/stnolting/neorv32/pull/1150
Minor rtl edits and cleanup; :bug: fix multiple drivers bug by @stnolting in https://github.com/stnolting/neorv32/pull/1151
[sw/bootloader] aligned trap handler by @LukasP46 in https://github.com/stnolting/neorv32/pull/1153
[top] add WDT and OCD reset outputs by @stnolting in https://github.com/stnolting/neorv32/pull/1152
✨ add GPIO interrupt(s) by @stnolting in https://github.com/stnolting/neorv32/pull/1159
[ci] update GHDL setup by @stnolting in https://github.com/stnolting/neorv32/pull/1160
Update neorv32ProcessorTopMinimalBoot.vhd by @ohenley in https://github.com/stnolting/neorv32/pull/1156
🐛 [twd] fix some design flaws by @stnolting in https://github.com/stnolting/neorv32/pull/1161
atomic memory access updates and improvements by @stnolting in https://github.com/stnolting/neorv32/pull/1163
[rtl] use past SDA in twd FSM transition by @LukasP46 in https://github.com/stnolting/neorv32/pull/1165

New Contributors

@ohenley made their first contribution in https://github.com/stnolting/neorv32/pull/1156

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.10.9...v1.11.0

- VHDL
Published by stnolting about 1 year ago

What's Changed

⚠️ Replace MTIME by CLINT by @stnolting in https://github.com/stnolting/neorv32/pull/1130
Add "out-of-band" signals to internal bus interface by @stnolting in https://github.com/stnolting/neorv32/pull/1131
Update neorv32cpucontrol.vhd by @mahdi259 in https://github.com/stnolting/neorv32/pull/1128
⚠️ rename SYSINFO.MEM -> SYSINFO.MISC by @stnolting in https://github.com/stnolting/neorv32/pull/1134
🧪 add multi-hart support to on-chip-debugger's debug module by @stnolting in https://github.com/stnolting/neorv32/pull/1132
[clint] automate MTIMECMP selection by @stnolting in https://github.com/stnolting/neorv32/pull/1136
⚠️ Move RTE information functions to AUX library by @stnolting in https://github.com/stnolting/neorv32/pull/1137
✨ add smp dual-core support by @stnolting in https://github.com/stnolting/neorv32/pull/1135
⚠️✨ replace Zalrsc ISA extension by Zaamo ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/1141
✨ [dual-core] add inter-core communication by @stnolting in https://github.com/stnolting/neorv32/pull/1142
[ci] workaround - ghdl installation by @stnolting in https://github.com/stnolting/neorv32/pull/1143
Minor rtl edits and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/1144

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.10.8...v1.10.9

- VHDL
Published by stnolting about 1 year ago

What's Changed

🧪 Shrink bootloader ISA and RAM requirements by @stnolting in https://github.com/stnolting/neorv32/pull/1118
[sim] rework default testbench by @stnolting in https://github.com/stnolting/neorv32/pull/1119
⚠️ rework TRNG by @stnolting in https://github.com/stnolting/neorv32/pull/1120
✨ add new module: device-mode I²C controller ("TWD") by @stnolting in https://github.com/stnolting/neorv32/pull/1121
Docs: removed Chapter about VHDL Development Environment by @vogma in https://github.com/stnolting/neorv32/pull/1122
🧪 [pmp] use time-multiplex approach by @stnolting in https://github.com/stnolting/neorv32/pull/1105
minor rtl cleanups and optimization by @stnolting in https://github.com/stnolting/neorv32/pull/1123
Relocate clock gating switch by @stnolting in https://github.com/stnolting/neorv32/pull/1124
⚠️ Rename CPU tuning options / generics by @stnolting in https://github.com/stnolting/neorv32/pull/1125
⚠️ Rework IO/peripheral address space by @stnolting in https://github.com/stnolting/neorv32/pull/1126

New Contributors

@vogma made their first contribution in https://github.com/stnolting/neorv32/pull/1122

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.10.7...v1.10.8

- VHDL
Published by stnolting about 1 year ago

What's Changed

⚠️ Relocate VUnit testbench to another sub-repository (neorv32-vunit) by @stnolting in https://github.com/stnolting/neorv32/pull/1083
[github workflow] remove packages by @stnolting in https://github.com/stnolting/neorv32/pull/1085
🧪 convert VHDL memory images into full-scale VHDL packages by @stnolting in https://github.com/stnolting/neorv32/pull/1084
⚠️ Rework processor boot configuration by @stnolting in https://github.com/stnolting/neorv32/pull/1086
Minor rtl edits and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/1090
Rework default testbench by @stnolting in https://github.com/stnolting/neorv32/pull/1093
🧪 Use xpack risc-v gcc as default prebuilt toolchain by @stnolting in https://github.com/stnolting/neorv32/pull/1091
[CPU control] large code cleanup by @stnolting in https://github.com/stnolting/neorv32/pull/1099
Fixed typo and cpu_alu architecture renaming for consistency by @LukasP46 in https://github.com/stnolting/neorv32/pull/1102
[docs/makefile] Copy figures also for single targets by @LukasP46 in https://github.com/stnolting/neorv32/pull/1101
[rtl] fix some Verilog [sic] issues by @stnolting in https://github.com/stnolting/neorv32/pull/1103
[sw] Use build folder and add example for more complex project structure by @LukasP46 in https://github.com/stnolting/neorv32/pull/1107
[TWI] add bus sensing logic by @stnolting in https://github.com/stnolting/neorv32/pull/1111
[sw] Add UART disable tag by @LukasP46 in https://github.com/stnolting/neorv32/pull/1112
✨ add ONEWIRE command FIFO; 🐛 fix ONEWIRE status flag by @stnolting in https://github.com/stnolting/neorv32/pull/1113
use vhdl 2008 standard in ghdl simulations by @csantosb in https://github.com/stnolting/neorv32/pull/1096
[docs] Fix missing " in makefile by @LukasP46 in https://github.com/stnolting/neorv32/pull/1117

New Contributors

@LukasP46 made their first contribution in https://github.com/stnolting/neorv32/pull/1102
@csantosb made their first contribution in https://github.com/stnolting/neorv32/pull/1096

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.10.6...v1.10.7

- VHDL
Published by stnolting about 1 year ago

What's Changed

:warning: rework CFU handshake interface by @stnolting in https://github.com/stnolting/neorv32/pull/1046
⚠️ remove A ISA extension, add Zalrsc ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/1047
Uprade neoTRNG to version 3.2 by @stnolting in https://github.com/stnolting/neorv32/pull/1048
:warning: rework PWM module by @stnolting in https://github.com/stnolting/neorv32/pull/1049
[ci] remove python doit by @stnolting in https://github.com/stnolting/neorv32/pull/1055
✨🔒 add optional on-chip debugger authentication by @stnolting in https://github.com/stnolting/neorv32/pull/1053
:warning: Remove OCD's DM legacy mode by @stnolting in https://github.com/stnolting/neorv32/pull/1056
[sw/lib] restore previous registers in neorv32xirqget_num function to avoid side effects by @donlon in https://github.com/stnolting/neorv32/pull/1057
[vivado ip] hide entire AXI-Stream interface in block diagram if disabled by @donlon in https://github.com/stnolting/neorv32/pull/1058
[rtl/system_integration] create individual module for AXI4 Lite bridge by @donlon in https://github.com/stnolting/neorv32/pull/1063
Update dhry_1.c by @mahdi259 in https://github.com/stnolting/neorv32/pull/1066
[vivado ip] reorganize Vivado IP GUI by @donlon in https://github.com/stnolting/neorv32/pull/1064
[rtl] minor RTL edits by @stnolting in https://github.com/stnolting/neorv32/pull/1068
[vivado ip] make m_axi (XBUS) interface optional by @donlon in https://github.com/stnolting/neorv32/pull/1067
⚠️ Rework XIRQ - remove "pending" register by @stnolting in https://github.com/stnolting/neorv32/pull/1071
🧪 Rework makefile/linker script memory configuration by @stnolting in https://github.com/stnolting/neorv32/pull/1072
[sw/common] Cleanup central makefile and linker script by @stnolting in https://github.com/stnolting/neorv32/pull/1077

New Contributors

@donlon made their first contribution in https://github.com/stnolting/neorv32/pull/1057
@mahdi259 made their first contribution in https://github.com/stnolting/neorv32/pull/1066

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.10.5...v1.10.6

- VHDL
Published by stnolting over 1 year ago

What's Changed

[rtl] signal renamings and cleanups to make the code more readable by @stnolting in https://github.com/stnolting/neorv32/pull/1026
:bug: fix minor bug in FPU MUL instruction by @stnolting in https://github.com/stnolting/neorv32/pull/1028
[rtl] remove redundant prog_buf by @NikLeberg in https://github.com/stnolting/neorv32/pull/1030
[rtl] fix generate spelling by @NikLeberg in https://github.com/stnolting/neorv32/pull/1031
[cpu] rework ALU instruction decoding and CPU co-processor interface by @stnolting in https://github.com/stnolting/neorv32/pull/1032
✨ [cpu] add support for RISC-V scalar cryptography ISA extensions by @stnolting in https://github.com/stnolting/neorv32/pull/1033
Fix typo trap table by @BEforlin in https://github.com/stnolting/neorv32/pull/1035
Add Zkt ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/1036
:sparkles: add support for RISC-V Zbkb ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/1037
✨ add support for RISC-V Zbkc ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/1038
Add Zkn ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/1039
✨ add support for RISC-V Zks* ISA extensions by @stnolting in https://github.com/stnolting/neorv32/pull/1040
⚠️ Rename CPU ISA configuration generics by @stnolting in https://github.com/stnolting/neorv32/pull/1041
:warning: split B ISA extension into individual sub-extensions by @stnolting in https://github.com/stnolting/neorv32/pull/1044

New Contributors

@BEforlin made their first contribution in https://github.com/stnolting/neorv32/pull/1035

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.10.4...v1.10.5

- VHDL
Published by stnolting over 1 year ago

What's Changed

minor RTL cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/1004
🧪 Remove "loop" from memory initialization function by @stnolting in https://github.com/stnolting/neorv32/pull/1005
minor fixes in OCD by @NikLeberg in https://github.com/stnolting/neorv32/pull/1006
[sw] fix sysinfo doxygen header by @NikLeberg in https://github.com/stnolting/neorv32/pull/1007
optimize CSR address logic by @stnolting in https://github.com/stnolting/neorv32/pull/1008
Minor rtl/CSR optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/1010
Cleanup debug symbols by @stnolting in https://github.com/stnolting/neorv32/pull/1009
minor HDL cleanups and otimizations by @stnolting in https://github.com/stnolting/neorv32/pull/1014
Cleanup and extend watch dog's reset-cause logic by @stnolting in https://github.com/stnolting/neorv32/pull/1015
⚠️ Refactor RTL files / hierarchy by @stnolting in https://github.com/stnolting/neorv32/pull/1017
:bug: fix B.CTZ decoding regression bug by @stnolting in https://github.com/stnolting/neorv32/pull/1018
Massive rtl code cleanup by @stnolting in https://github.com/stnolting/neorv32/pull/1019
:bug: fix stack alignment upon first procedure entry by @stnolting in https://github.com/stnolting/neorv32/pull/1021

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.10.3...v1.10.4

- VHDL
Published by stnolting over 1 year ago

What's Changed

⚠️ rework CFU (remove R5-type instructions) by @stnolting in https://github.com/stnolting/neorv32/pull/971
Rework (and auto-generate) file-list files by @stnolting in https://github.com/stnolting/neorv32/pull/972
[docs] fix spelling by @NikLeberg in https://github.com/stnolting/neorv32/pull/975
[vivado_ip] fix error when AXI port is unconnected by @stnolting in https://github.com/stnolting/neorv32/pull/976
[vivado_ip] fix unconnected variable-size inputs by @stnolting in https://github.com/stnolting/neorv32/pull/978
[vivado_ip] constrain minimal size of variable-sized output ports by @stnolting in https://github.com/stnolting/neorv32/pull/980
Minor RTL edits by @stnolting in https://github.com/stnolting/neorv32/pull/984
:warning: reorganize core RTL files :warning: by @stnolting in https://github.com/stnolting/neorv32/pull/985
[rtl] minor timing and area optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/990
RTL reworks, cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/996
:bug: fix minor regression bug; minor RTL optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/998

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.10.2...v1.10.3

- VHDL
Published by stnolting over 1 year ago

What's Changed

minor software framework cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/940
minor rtl cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/941
minor rtl edits by @stnolting in https://github.com/stnolting/neorv32/pull/948
[image_generator] add *.mif memory initialization file format by @stnolting in https://github.com/stnolting/neorv32/pull/949
Add option to disable SYSINFO module by @stnolting in https://github.com/stnolting/neorv32/pull/952
🐛 Fix SDI "TX FIFO full" flag by @stnolting in https://github.com/stnolting/neorv32/pull/953
[SPI] add programmable chip-select operations by @stnolting in https://github.com/stnolting/neorv32/pull/954
Minor SDI edits by @stnolting in https://github.com/stnolting/neorv32/pull/955
🐛 [newlib] fix broken sbrk function by @stnolting in https://github.com/stnolting/neorv32/pull/957
[rtl] clean-up simulation-only pragmas by @stnolting in https://github.com/stnolting/neorv32/pull/956
🔒 restrict access to IO modules to privileged (machine-mode) software by @stnolting in https://github.com/stnolting/neorv32/pull/958
Minor SW framework edits to fix c++ warnings by @stnolting in https://github.com/stnolting/neorv32/pull/964
Make SYSINFO CLK writable by @stnolting in https://github.com/stnolting/neorv32/pull/966

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.10.1...v1.10.2

- VHDL
Published by stnolting over 1 year ago

What's Changed

⚠️ remove redundant JTAG reset signal (TRST) by @stnolting in https://github.com/stnolting/neorv32/pull/928
minor rtl code clean-ups by @stnolting in https://github.com/stnolting/neorv32/pull/929
Add UART FIFO clear flags; add DMA FIRQ interrupt configuration by @stnolting in https://github.com/stnolting/neorv32/pull/930
Minor rtl edits/cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/931
:warning: rework CFU interface by @stnolting in https://github.com/stnolting/neorv32/pull/932
minor software updates and fixes by @stnolting in https://github.com/stnolting/neorv32/pull/933
[sw] add auxiliary/helper functions library by @stnolting in https://github.com/stnolting/neorv32/pull/934
minor rtl edits and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/935
Minor sw & hw cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/936
🧪 Add experimental XBUS (Wishbone) to AHB3-Lite bridge by @stnolting in https://github.com/stnolting/neorv32/pull/937
⚠️ Remove AMORVSGRANULARITY generic by @stnolting in https://github.com/stnolting/neorv32/pull/938
⚠️ rework GPTMR by @stnolting in https://github.com/stnolting/neorv32/pull/939

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.10.0...v1.10.1

- VHDL
Published by stnolting over 1 year ago

What's Changed

Add NEORV32 as Vivado IP by @stnolting in https://github.com/stnolting/neorv32/pull/894
Cleanup SW library by @stnolting in https://github.com/stnolting/neorv32/pull/900
Add back Dhrystone port by @stnolting in https://github.com/stnolting/neorv32/pull/901
Update neorv32_sdi.vhd - Minor typo correction by @ucycg in https://github.com/stnolting/neorv32/pull/903
Add COE and MEM file generator options by @stnolting in https://github.com/stnolting/neorv32/pull/904
[FPU] prevent GCC from emitting fused multiply-add instructions by @stnolting in https://github.com/stnolting/neorv32/pull/905
Add SLINK routing information ports by @stnolting in https://github.com/stnolting/neorv32/pull/908
Make XIRQ trigger configuration programmable by @stnolting in https://github.com/stnolting/neorv32/pull/911
Add HDL file list files by @stnolting in https://github.com/stnolting/neorv32/pull/909
Relocate f files by @stnolting in https://github.com/stnolting/neorv32/pull/912
Add variable-sized ports to Vivado IP block by @stnolting in https://github.com/stnolting/neorv32/pull/913
Fix uncached/cached access priority by @stnolting in https://github.com/stnolting/neorv32/pull/915
[xbus] access type identifier (tag signal) by @stnolting in https://github.com/stnolting/neorv32/pull/917
[sw/lib] :warning: rework gpiopinset function by @stnolting in https://github.com/stnolting/neorv32/pull/921
[rtl] TRNG: add data-available interrupt by @stnolting in https://github.com/stnolting/neorv32/pull/922
Minor code cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/925
:sparkles: Add pre-configured Eclipse example project by @stnolting in https://github.com/stnolting/neorv32/pull/926

New Contributors

@ucycg made their first contribution in https://github.com/stnolting/neorv32/pull/903

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.9.9...v1.10.0

- VHDL
Published by stnolting over 1 year ago

What's Changed

minor rtl clean-ups and optimization by @stnolting in https://github.com/stnolting/neorv32/pull/872
use simplified VHDL file headers by @stnolting in https://github.com/stnolting/neorv32/pull/873
:warning: rename SLINK data interface registers by @stnolting in https://github.com/stnolting/neorv32/pull/874
:warning: simplify XBUS gateway by @stnolting in https://github.com/stnolting/neorv32/pull/876
[DMA] use FIRQ select instead of FIRQ mask by @stnolting in https://github.com/stnolting/neorv32/pull/877
rtl logic optimization and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/880
fix external debug-halt vs. exception concurrency by @stnolting in https://github.com/stnolting/neorv32/pull/882
minor rtl fixes by @stnolting in https://github.com/stnolting/neorv32/pull/883
[rtl] fix single-step halting by @stnolting in https://github.com/stnolting/neorv32/pull/887
minor rtl cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/889
Fix UART receiver by @Unike267 in https://github.com/stnolting/neorv32/pull/891

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.9.8...v1.9.9

- VHDL
Published by stnolting almost 2 years ago

What's Changed

CPU RTL optimization by @stnolting in https://github.com/stnolting/neorv32/pull/857
:warning: remove WDT + TRNG interrupts; :bug: fix bug in core-complex clocking during sleep by @stnolting in https://github.com/stnolting/neorv32/pull/858
:warning: rework ONEWIRE and GPTMR interrupts by @stnolting in https://github.com/stnolting/neorv32/pull/859
:warning: rework TWI interrupt by @stnolting in https://github.com/stnolting/neorv32/pull/860
:bug: fix DMA fence flag, :warning: rework CPU FIRQs by @stnolting in https://github.com/stnolting/neorv32/pull/864
Support tool-specific standard flags in makefile by @jpf91 in https://github.com/stnolting/neorv32/pull/862
:warning: rework TWI module by @stnolting in https://github.com/stnolting/neorv32/pull/865
add back TWI clock stretching option by @stnolting in https://github.com/stnolting/neorv32/pull/867
[SLINK] split interrupt into two FIRQs by @stnolting in https://github.com/stnolting/neorv32/pull/868
B ISA extensions only contains Zba + Zbb + Zbs by @stnolting in https://github.com/stnolting/neorv32/pull/869
add additional SPI and SDI interrupt conditions by @stnolting in https://github.com/stnolting/neorv32/pull/870

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.9.7...v1.9.8

- VHDL
Published by stnolting almost 2 years ago

What's Changed

[rtl] add generic cache module (not used yet) by @stnolting in https://github.com/stnolting/neorv32/pull/842
rtl cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/843
⚠️ remove Wishbone tag signal by @stnolting in https://github.com/stnolting/neorv32/pull/845
⚠️⚠️ Rename external bus interface by @stnolting in https://github.com/stnolting/neorv32/pull/846
✨ Add optional external bus interface cache (XCACHE) by @stnolting in https://github.com/stnolting/neorv32/pull/849
:warning: processor configuration edits / clean-ups by @stnolting in https://github.com/stnolting/neorv32/pull/850
Minor cache updates by @stnolting in https://github.com/stnolting/neorv32/pull/851
[litex] update core complex wrapper by @stnolting in https://github.com/stnolting/neorv32/pull/852
rework cache system by @stnolting in https://github.com/stnolting/neorv32/pull/853
Connected SPI bus to on-board Flash and SPI peripheral by @lovelesh-mis in https://github.com/stnolting/neorv32/pull/854
Update CFU example: use XTEA as "real world" demo application by @stnolting in https://github.com/stnolting/neorv32/pull/855
Updated Performance test by @mikaelsky in https://github.com/stnolting/neorv32/pull/844

New Contributors

@lovelesh-mis made their first contribution in https://github.com/stnolting/neorv32/pull/854

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.9.6...v1.9.7

- VHDL
Published by stnolting almost 2 years ago

What's Changed

Allow disabling certain PMP modes by @stnolting in https://github.com/stnolting/neorv32/pull/808
[revert] remove page faults support by @stnolting in https://github.com/stnolting/neorv32/pull/809
:bug: Fix bug in CRT0 trap handler by @stnolting in https://github.com/stnolting/neorv32/pull/812
:warning: Rework hardware performance monitor (HPM) events by @stnolting in https://github.com/stnolting/neorv32/pull/811
🧪 [makefile] pass CC_OPTS variable as define string by @stnolting in https://github.com/stnolting/neorv32/pull/813
⚠️ remove Smcntrpmf ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/814
[sim] add simulation check to sw makefiles as target 'sim-check' by @umarcor in https://github.com/stnolting/neorv32/pull/817
[SLINK] add AXI-stream-compatible "tlast" signals by @stnolting in https://github.com/stnolting/neorv32/pull/815
[docs/userguide/simulatingtheprocessor] add admonition and recommend MARCH=rv32im to build hello_world by @umarcor in https://github.com/stnolting/neorv32/pull/819
[ci] split SoftwareFrameworkTests from simple testbench simulation by @umarcor in https://github.com/stnolting/neorv32/pull/820
🐛 Fix write access to mip.firq CSR bits by @stnolting in https://github.com/stnolting/neorv32/pull/821
[ci] test example hello_world as well by @umarcor in https://github.com/stnolting/neorv32/pull/822
[fifo] fix (Vivado) synthesis issue by @stnolting in https://github.com/stnolting/neorv32/pull/827
optimize FIFO component to improve mapping by @stnolting in https://github.com/stnolting/neorv32/pull/828
Added dummy clocks for SLINK streams in AXI4-Lite wrapper by @robhancocksed in https://github.com/stnolting/neorv32/pull/831
:bug: fix atomic write/clear/set accesses of clear-only CSR bits by @stnolting in https://github.com/stnolting/neorv32/pull/829
[sw] remove unused variable RISCV_TOOLCHAIN by @umarcor in https://github.com/stnolting/neorv32/pull/832
:bug: fix GPTMR threshold = 0 configuration by @stnolting in https://github.com/stnolting/neorv32/pull/834
Small correction in user guide by @davidgussler in https://github.com/stnolting/neorv32/pull/835

New Contributors

@robhancocksed made their first contribution in https://github.com/stnolting/neorv32/pull/831
@davidgussler made their first contribution in https://github.com/stnolting/neorv32/pull/835

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.9.5...v1.9.6

- VHDL
Published by stnolting almost 2 years ago

What's Changed

fix trap priority by @stnolting in https://github.com/stnolting/neorv32/pull/784
Add support for page fault exceptions by @stnolting in https://github.com/stnolting/neorv32/pull/786
[cpu] fix minor bug in instruction request bus by @stnolting in https://github.com/stnolting/neorv32/pull/790
Fix for issue #785: FPU fflags no being asserted correctly by @mikaelsky in https://github.com/stnolting/neorv32/pull/788
🐛 [cpu] fix non-stable privilege signal of instruction interface by @stnolting in https://github.com/stnolting/neorv32/pull/792
[CPU] close further illegal instruction loopholes by @stnolting in https://github.com/stnolting/neorv32/pull/797
✨ add optional XIP cache by @stnolting in https://github.com/stnolting/neorv32/pull/799
add fence signal to CPU bus by @stnolting in https://github.com/stnolting/neorv32/pull/800
:bug: fix fence signal pass-through in caches by @stnolting in https://github.com/stnolting/neorv32/pull/802
[rtl] fix HPM null range assertions by @stnolting in https://github.com/stnolting/neorv32/pull/803
minor rtl edits by @stnolting in https://github.com/stnolting/neorv32/pull/804
Fixes to the FPU for issue #791 by @mikaelsky in https://github.com/stnolting/neorv32/pull/794
:bug: fix another C-ISA loophole by @stnolting in https://github.com/stnolting/neorv32/pull/806
Add DMA fence operation by @stnolting in https://github.com/stnolting/neorv32/pull/807

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.9.4...v1.9.5

- VHDL
Published by stnolting about 2 years ago

What's Changed

[rtl] minor cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/764
[rtl] optimize bus switch by @stnolting in https://github.com/stnolting/neorv32/pull/769
:bug: Remove RVC float load/store instructions by @stnolting in https://github.com/stnolting/neorv32/pull/771
✨ add optional CPU clock gating by @stnolting in https://github.com/stnolting/neorv32/pull/775
:bug: fix typo that renders the clock gating useless by @stnolting in https://github.com/stnolting/neorv32/pull/776
[rtl] improve CPU front end by @stnolting in https://github.com/stnolting/neorv32/pull/777
Updated FIFO NULL assertion fix by @mikaelsky in https://github.com/stnolting/neorv32/pull/778
set top entiy input defaults to 'L' or 'H' by @stnolting in https://github.com/stnolting/neorv32/pull/779
🧪 extend switchable clock domain by @stnolting in https://github.com/stnolting/neorv32/pull/780
Fix for issue #782 by @mikaelsky in https://github.com/stnolting/neorv32/pull/783

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.9.3...v1.9.4

- VHDL
Published by stnolting about 2 years ago

What's Changed

✨ Add RISC-V Zicond ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/743
[rtl] reset mstatus.mpp to machine-mode by @stnolting in https://github.com/stnolting/neorv32/pull/745
refine behaviour of CPU sleep signal by @stnolting in https://github.com/stnolting/neorv32/pull/746
[rtl] minor rtl code cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/747
[sw] Clean-up software framework by @stnolting in https://github.com/stnolting/neorv32/pull/752
[rtl] rework FIFO module (to allow inferring block RAM) by @stnolting in https://github.com/stnolting/neorv32/pull/754
[rtl] minor edits, clean-ups and optimizations; 🔒 set mepc/mtvec/dpc reset value to CPU boot address by @stnolting in https://github.com/stnolting/neorv32/pull/755
Add GPTMR timer capture by @stnolting in https://github.com/stnolting/neorv32/pull/759
[rtl] minor code cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/760
[rtl/core] add again mtime_o to top entity by @mcoroyer in https://github.com/stnolting/neorv32/pull/762
[rtl] fix minor VHDL coding style issue by @stnolting in https://github.com/stnolting/neorv32/pull/763

New Contributors

@mcoroyer made their first contribution in https://github.com/stnolting/neorv32/pull/762

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.9.2...v1.9.3

- VHDL
Published by stnolting about 2 years ago

What's Changed

Fix comment mistake by @Unike267 in https://github.com/stnolting/neorv32/pull/727
[SPI] re-add high-speed mode by @stnolting in https://github.com/stnolting/neorv32/pull/730
[XIP] add clock divider for fine-tuning by @stnolting in https://github.com/stnolting/neorv32/pull/731
🐛 [FPU] fix wiring of exception flags by @stnolting in https://github.com/stnolting/neorv32/pull/733
🐛 fix bug in instruction-misaligned exception handling by @stnolting in https://github.com/stnolting/neorv32/pull/734
[rtl] cleanup & rework/optimize CPU branch system by @stnolting in https://github.com/stnolting/neorv32/pull/735
✨ Add "ASIC style" register file option by @stnolting in https://github.com/stnolting/neorv32/pull/736
[rtl] Cleanup/update assertions and "auto-configuration" by @stnolting in https://github.com/stnolting/neorv32/pull/738
Update hardware tigger module (Sdtrig) to version 1.0 by @stnolting in https://github.com/stnolting/neorv32/pull/739
Add menvcfg[h] CSRs by @stnolting in https://github.com/stnolting/neorv32/pull/741
[RTE] minor updates by @stnolting in https://github.com/stnolting/neorv32/pull/742

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.9.1...v1.9.2

- VHDL
Published by stnolting about 2 years ago

What's Changed

Update software framework to gcc-13.2.0 by @stnolting in https://github.com/stnolting/neorv32/pull/705
[cpu] minor cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/707
⚠️ remove Zifencei generic - Zifencei ISA extension is now always enabled by @stnolting in https://github.com/stnolting/neorv32/pull/709
[sw/lib] add nerov32-flavored vprintf funtion by @stnolting in https://github.com/stnolting/neorv32/pull/711
[sim] Add GHDL run flags variable by @stnolting in https://github.com/stnolting/neorv32/pull/715
Move FreeRTOS port & demo into new repository by @stnolting in https://github.com/stnolting/neorv32/pull/716
Fix bug in neorv32slinkavailable() function by @Unike267 in https://github.com/stnolting/neorv32/pull/717
[rtl] cleanups and code beautification by @stnolting in https://github.com/stnolting/neorv32/pull/718
[sw] update crt0's early-boot trap handler by @stnolting in https://github.com/stnolting/neorv32/pull/719
[rtl] upgrade neoTRNG to version 3 by @stnolting in https://github.com/stnolting/neorv32/pull/721
Fix-up the litex wrapper by @Unike267 in https://github.com/stnolting/neorv32/pull/722
minor rtl code cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/723
🧪 provide full hardware reset for all FFs by @stnolting in https://github.com/stnolting/neorv32/pull/724

New Contributors

@Unike267 made their first contribution in https://github.com/stnolting/neorv32/pull/717

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.9.0...v1.9.1

- VHDL
Published by stnolting over 2 years ago

What's Changed

minor rtl edits by @stnolting in https://github.com/stnolting/neorv32/pull/684
Minor rtl edits by @stnolting in https://github.com/stnolting/neorv32/pull/690
rework watchdog timer and reset system by @stnolting in https://github.com/stnolting/neorv32/pull/692
implement vectored mtvec by @NikLeberg in https://github.com/stnolting/neorv32/pull/691
Minor rtl optimizations and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/694
[PMP] logic optimization by @stnolting in https://github.com/stnolting/neorv32/pull/695
[SW] Warning removed of unused variable by @emb4fun in https://github.com/stnolting/neorv32/pull/696
:warning: rework SoC bus protocol by @stnolting in https://github.com/stnolting/neorv32/pull/697
[SW] Illegal instruction removed by @emb4fun in https://github.com/stnolting/neorv32/pull/698
[dma] add "transfer done" flag by @stnolting in https://github.com/stnolting/neorv32/pull/699
Update correct file by @lianakoleva in https://github.com/stnolting/neorv32/pull/702
minor edits and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/703
Match existing filename by @lianakoleva in https://github.com/stnolting/neorv32/pull/704

New Contributors

@lianakoleva made their first contribution in https://github.com/stnolting/neorv32/pull/702

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.8.9...v1.9.0

- VHDL
Published by stnolting over 2 years ago

What's Changed

Update RTE to support easy emulation of instructions by @stnolting in https://github.com/stnolting/neorv32/pull/673
⚠️ constrain MTVAL CSR, add MTINST CSR by @stnolting in https://github.com/stnolting/neorv32/pull/674
Add Smcntrpmf ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/676
[OCD] add option to select DM legacy mode by @stnolting in https://github.com/stnolting/neorv32/pull/677
[cpu] remove branch prediction logic by @stnolting in https://github.com/stnolting/neorv32/pull/678
minor rtl edits and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/679
[cpu] add execution monitor by @stnolting in https://github.com/stnolting/neorv32/pull/680
[CFU] add support for CFU-internal CSRs by @stnolting in https://github.com/stnolting/neorv32/pull/681
CPU hardware optimization by @stnolting in https://github.com/stnolting/neorv32/pull/683

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.8.8...v1.8.9

- VHDL
Published by stnolting over 2 years ago

What's Changed

⚠️ Remove CUSTOM_ID generic by @stnolting in https://github.com/stnolting/neorv32/pull/657
🐛 Make sure IMEM/DMEM sizes are a power of two by @stnolting in https://github.com/stnolting/neorv32/pull/658
:warning: Rework SYSINFO module by @stnolting in https://github.com/stnolting/neorv32/pull/659
[rtl] Cleanups and Optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/660
⚠️ Major code edits / cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/664
[rtl] fix natural condition by @NikLeberg in https://github.com/stnolting/neorv32/pull/665
minor cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/669
Remove Zicond ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/670
⚠️ Constrain/optimize MTVAL and MCOUNTEREN CSRs by @stnolting in https://github.com/stnolting/neorv32/pull/671
[rtl] minor edits and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/672

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.8.7...v1.8.8

- VHDL
Published by stnolting over 2 years ago

What's Changed

demoblinkled_asm bugfix by @vivi202 in https://github.com/stnolting/neorv32/pull/639
Minor rtl edits, cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/641
Minor rtl edits by @stnolting in https://github.com/stnolting/neorv32/pull/646
⚠️ Rework SoC bus system and memory map by @stnolting in https://github.com/stnolting/neorv32/pull/648
⚠️ Remove UART sim-mode's 32-bit dump by @stnolting in https://github.com/stnolting/neorv32/pull/650
✨ Add support for RISC-V A ISA extension (atomic memory access) by @stnolting in https://github.com/stnolting/neorv32/pull/651
Minor rtl edits by @stnolting in https://github.com/stnolting/neorv32/pull/652
[rtl] Optimize bus system and customization options by @stnolting in https://github.com/stnolting/neorv32/pull/653
:bug: fixing some LR/SC design flaws by @stnolting in https://github.com/stnolting/neorv32/pull/654

New Contributors

@vivi202 made their first contribution in https://github.com/stnolting/neorv32/pull/639

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.8.6...v1.8.7

- VHDL
Published by stnolting over 2 years ago

What's Changed

[TRNG] software can now retrieve FIFO size by @stnolting in https://github.com/stnolting/neorv32/pull/616
[DMA] add automatic trigger mode by @stnolting in https://github.com/stnolting/neorv32/pull/618
🐛 [linker script] fix section continuity issue by @stnolting in https://github.com/stnolting/neorv32/pull/626
[SYSINFO] re-arrange bits by @stnolting in https://github.com/stnolting/neorv32/pull/627
✨ Re-add simplified stream link interface (SLINK) by @stnolting in https://github.com/stnolting/neorv32/pull/628
:sparkles: add CRC unit by @stnolting in https://github.com/stnolting/neorv32/pull/632
[makefile] extend GDB target by @stnolting in https://github.com/stnolting/neorv32/pull/634
⚠️ remove BUSKEEPER's status register by @stnolting in https://github.com/stnolting/neorv32/pull/635
optimize CPU's control logic by @stnolting in https://github.com/stnolting/neorv32/pull/636
🧪 VHDL - use entity instantiation by @stnolting in https://github.com/stnolting/neorv32/pull/637

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.8.5...v1.8.6

- VHDL
Published by stnolting over 2 years ago

What's Changed

✨ add optional direct memory access controller (DMA) by @stnolting in https://github.com/stnolting/neorv32/pull/593
[rtl] minor edits by @stnolting in https://github.com/stnolting/neorv32/pull/599
🐛 [rtl] fix bug in DMA by @stnolting in https://github.com/stnolting/neorv32/pull/601
[rtl] minor edits; update to VUnit v5 by @stnolting in https://github.com/stnolting/neorv32/pull/605
[rtl] rework SoC bus system by @stnolting in https://github.com/stnolting/neorv32/pull/607
[rtl] minor rtl updates by @stnolting in https://github.com/stnolting/neorv32/pull/608
🐛 [FPU] fix bug in FPU trap handling by @stnolting in https://github.com/stnolting/neorv32/pull/609
[CPU] move instruction address to mtval on ebreak exception by @stnolting in https://github.com/stnolting/neorv32/pull/611
Add programmable TRNG interrupt by @stnolting in https://github.com/stnolting/neorv32/pull/615

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.8.4...v1.8.5

- VHDL
Published by stnolting almost 3 years ago

What's Changed

[PMP] add support for NA4 and NAPOT modes by @stnolting in https://github.com/stnolting/neorv32/pull/566
[rtl] cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/569
update XIRQ controller by @stnolting in https://github.com/stnolting/neorv32/pull/570
[rtl] coding style edits and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/571
Remove warnings by @emb4fun in https://github.com/stnolting/neorv32/pull/561
Updated path for FreeRTOS example - FreeRTOS-Plus-TCP by @matty0005 in https://github.com/stnolting/neorv32/pull/574
🐛 FPU bug fix and rtl optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/578
[UART] add FIFO configuration to DATA register by @stnolting in https://github.com/stnolting/neorv32/pull/581
🐛⚠️ CPU bug-fixes, major cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/586
Freertos xirq example by @matty0005 in https://github.com/stnolting/neorv32/pull/585
[rtl] minor optimizations/cleanups of processor bus system by @stnolting in https://github.com/stnolting/neorv32/pull/591
Added a test case to show the 1.0 + -1.0 instruction time-out under f… by @mikaelsky in https://github.com/stnolting/neorv32/pull/592

New Contributors

@matty0005 made their first contribution in https://github.com/stnolting/neorv32/pull/574

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.8.3...v1.8.4

- VHDL
Published by stnolting almost 3 years ago

What's Changed

[rtl] minor edits, cleanups and optimization by @stnolting in https://github.com/stnolting/neorv32/pull/545
[sw/lib] move register and bit definitions to according module header files by @emb4fun in https://github.com/stnolting/neorv32/pull/542
✨ add support for RISC-V 'Zicond' ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/546
[docs] rework, update and cleanup entire documentation by @stnolting in https://github.com/stnolting/neorv32/pull/549
Added support for USER_LIBS in the command SW makefile. by @vhdlnerd in https://github.com/stnolting/neorv32/pull/551
[sw] bootloader: send wake up command to flash before trying to speak with it by @agamez in https://github.com/stnolting/neorv32/pull/552
[rtl] reworks, cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/550
[sw/example] demo_twi: remove comment requiring PWM module by @agamez in https://github.com/stnolting/neorv32/pull/554
[sw/lib] move CSR definitions to separate file by @stnolting in https://github.com/stnolting/neorv32/pull/553
[rtl] re-add VHDL process names by @stnolting in https://github.com/stnolting/neorv32/pull/555
✨ add time[h] CSRs by @stnolting in https://github.com/stnolting/neorv32/pull/556
[rtl] cleanup top's generics by @stnolting in https://github.com/stnolting/neorv32/pull/557
[rtl] cleanup, reworks and optimization by @stnolting in https://github.com/stnolting/neorv32/pull/559
🧪 Add processor data cache by @stnolting in https://github.com/stnolting/neorv32/pull/560
⚠️ [rtl] remove Zicsr generic, cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/562
Bootloader Config Parameter to Enable UART0 HW Handshaking. by @vhdlnerd in https://github.com/stnolting/neorv32/pull/565

New Contributors

@vhdlnerd made their first contribution in https://github.com/stnolting/neorv32/pull/551
@agamez made their first contribution in https://github.com/stnolting/neorv32/pull/552

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.8.2...v1.8.3

- VHDL
Published by stnolting almost 3 years ago

What's Changed

[CFS] add another 64 interface registers by @stnolting in https://github.com/stnolting/neorv32/pull/503
:warning: rename SPI & XIP module's top interface ports by @stnolting in https://github.com/stnolting/neorv32/pull/504
Corrected the PWM address which was a typo. by @emb4fun in https://github.com/stnolting/neorv32/pull/506
✨ add SDI module (SPI device-class interface) by @stnolting in https://github.com/stnolting/neorv32/pull/505
GPTMR: Change "variable style" by "pointer style" by @emb4fun in https://github.com/stnolting/neorv32/pull/511
MTIME: Change "variable style" by "pointer style" by @emb4fun in https://github.com/stnolting/neorv32/pull/512
NEOLED: Change "variable style" by "pointer style" by @emb4fun in https://github.com/stnolting/neorv32/pull/513
GPIO: Change "variable style" by "pointer style" by @emb4fun in https://github.com/stnolting/neorv32/pull/510
ONEWIRE: Change "variable style" by "pointer style" by @emb4fun in https://github.com/stnolting/neorv32/pull/514
PWM: Change "variable style" by "pointer style" by @emb4fun in https://github.com/stnolting/neorv32/pull/515
SDI: Change "variable style" by "pointer style" by @emb4fun in https://github.com/stnolting/neorv32/pull/516
SPI: Change "variable style" by "pointer style" by @emb4fun in https://github.com/stnolting/neorv32/pull/517
TRNG: Change "variable style" by "pointer style" by @emb4fun in https://github.com/stnolting/neorv32/pull/518
TWI: Change "variable style" by "pointer style" by @emb4fun in https://github.com/stnolting/neorv32/pull/519
WDT: Change "variable style" by "pointer style" by @emb4fun in https://github.com/stnolting/neorv32/pull/520
XIP: Change "variable style" by "pointer style" by @emb4fun in https://github.com/stnolting/neorv32/pull/521
XIRQ: Change "variable style" by "pointer style" by @emb4fun in https://github.com/stnolting/neorv32/pull/522
CFS: Change "variable style" by "pointer style" by @emb4fun in https://github.com/stnolting/neorv32/pull/523
DM: Change "variable style" by "pointer style" by @emb4fun in https://github.com/stnolting/neorv32/pull/524
BUSKEEPER: Change "variable style" by "pointer style" by @emb4fun in https://github.com/stnolting/neorv32/pull/525
Removed unused defines IOREGx and IOROMx by @emb4fun in https://github.com/stnolting/neorv32/pull/527
SYSINFO: Change "variable style" by "pointer style" by @emb4fun in https://github.com/stnolting/neorv32/pull/526
Added test case in sw/example to demonstrate floating point normalize… by @mikaelsky in https://github.com/stnolting/neorv32/pull/528
[rtl] minor GPTMR code reworks by @stnolting in https://github.com/stnolting/neorv32/pull/529
Common neorv32 uart functions by @akaeba in https://github.com/stnolting/neorv32/pull/509
[sw/uart] allow for escaped percent sign by @NikLeberg in https://github.com/stnolting/neorv32/pull/531
:warning: Update / rework SPI module by @stnolting in https://github.com/stnolting/neorv32/pull/530
SVD: Corrected typo by @emb4fun in https://github.com/stnolting/neorv32/pull/532
⚠️ rework UART modules by @stnolting in https://github.com/stnolting/neorv32/pull/533
Update NEOLED module by @stnolting in https://github.com/stnolting/neorv32/pull/536
[UART] re-integrate RTS/CTS hardware flow-control by @stnolting in https://github.com/stnolting/neorv32/pull/541
[rtl] move ONEWIRE and TWI tri-state drivers out of core by @stnolting in https://github.com/stnolting/neorv32/pull/543

New Contributors

@mikaelsky made their first contribution in https://github.com/stnolting/neorv32/pull/528

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.8.1...v1.8.2

- VHDL
Published by stnolting almost 3 years ago

What's Changed

[docs] add note about platform specific DTMs by @NikLeberg in https://github.com/stnolting/neorv32/pull/482
💄 [docs] update/rework figures by @stnolting in https://github.com/stnolting/neorv32/pull/483
[rtl] Cleanup CPU interrupt controller by @stnolting in https://github.com/stnolting/neorv32/pull/484
[rtl] rework mip csr by @stnolting in https://github.com/stnolting/neorv32/pull/486
[rtl] CPU control optimization by @stnolting in https://github.com/stnolting/neorv32/pull/487
[rtl] CPU: use record as main control bus type by @stnolting in https://github.com/stnolting/neorv32/pull/489
[rtl] add co-processor timing monitor by @stnolting in https://github.com/stnolting/neorv32/pull/490
[sw/lib/include/neorv32.h]: remove redundant uart typedef by @akaeba in https://github.com/stnolting/neorv32/pull/493
⚠️ Replace IOGPIOEN generic by @stnolting in https://github.com/stnolting/neorv32/pull/491
[rtl] minor trap logic optimizations and fixes by @stnolting in https://github.com/stnolting/neorv32/pull/497
Add run.py dump of VHDL-LS library mapping by @kraigher in https://github.com/stnolting/neorv32/pull/494
[sw] add '_zicsr' to default MARCH configuration by @stnolting in https://github.com/stnolting/neorv32/pull/496
🐛 [rtl] fix bug in co-processor monitor by @stnolting in https://github.com/stnolting/neorv32/pull/500
⚠️ constrain & relocate PWM module by @stnolting in https://github.com/stnolting/neorv32/pull/501
:warning: remove SLINK module by @stnolting in https://github.com/stnolting/neorv32/pull/502

New Contributors

@NikLeberg made their first contribution in https://github.com/stnolting/neorv32/pull/482
@kraigher made their first contribution in https://github.com/stnolting/neorv32/pull/494

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.8.0...v1.8.1

- VHDL
Published by stnolting almost 3 years ago

What's Changed

Remove signal initalizations by @tmeissner in https://github.com/stnolting/neorv32/pull/464
Upgrade on-chip-debugger by @stnolting in https://github.com/stnolting/neorv32/pull/463
⚠️ rework CPU debug spec ISA configuration; ✨ enhance trigger module by @stnolting in https://github.com/stnolting/neorv32/pull/465
[sw] rename library functions by @stnolting in https://github.com/stnolting/neorv32/pull/467
[rtl] OCD: update DTM and DM by @stnolting in https://github.com/stnolting/neorv32/pull/468
Fix value of SYSINFOSOCIOONEWIRE in NEORV32SYSINFOSOCenum by @tmeissner in https://github.com/stnolting/neorv32/pull/469
[rtl] CPU: logic optimization by @stnolting in https://github.com/stnolting/neorv32/pull/470
[sw/example/demospiirq]: make read/write data pointer and busy flag… by @akaeba in https://github.com/stnolting/neorv32/pull/471
[rtl] update TRNG by @stnolting in https://github.com/stnolting/neorv32/pull/472
[rtl/test_setups] add on-chip debugger test setup by @stnolting in https://github.com/stnolting/neorv32/pull/473
:warning: rework watchdog timer (WDT) by @stnolting in https://github.com/stnolting/neorv32/pull/474
[rtl] VHDL cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/476
:warning: Rework CPU counters by @stnolting in https://github.com/stnolting/neorv32/pull/477
[sw] cleanup and update software framework by @stnolting in https://github.com/stnolting/neorv32/pull/478

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.7.9...v1.8.0

- VHDL
Published by stnolting about 3 years ago

What's Changed

[rtl] cleanup main package file by @stnolting in https://github.com/stnolting/neorv32/pull/447
[sw] rework intrinsic libraries by @stnolting in https://github.com/stnolting/neorv32/pull/448
✨ Add CFU R4-type instructions by @stnolting in https://github.com/stnolting/neorv32/pull/449
🐛 [rtl] core trap fixes by @stnolting in https://github.com/stnolting/neorv32/pull/450
[sw] Remove B ISA extension intrinsic library by @stnolting in https://github.com/stnolting/neorv32/pull/451
✨ [CFU] add support for custom R5-type instructions by @stnolting in https://github.com/stnolting/neorv32/pull/452
[rtl] instruction prefetch buffer (IPB) improvements by @stnolting in https://github.com/stnolting/neorv32/pull/455
🧪 [OCD] optimize firmware (park-loop) by @stnolting in https://github.com/stnolting/neorv32/pull/456
🐛 [rtl] fix iCache block error bug by @stnolting in https://github.com/stnolting/neorv32/pull/457
🐛 [rtl] fix MEPC value for instruction access faults by @stnolting in https://github.com/stnolting/neorv32/pull/458
[rtl] mtval CSR is now r/w by @stnolting in https://github.com/stnolting/neorv32/pull/460
[rt] SoC: rework r/w access logic and reset by @stnolting in https://github.com/stnolting/neorv32/pull/461
[rtl] CPU: optimizations and cleanup by @stnolting in https://github.com/stnolting/neorv32/pull/462

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.7.8...v1.7.9

- VHDL
Published by stnolting about 3 years ago

What's Changed

🐛 [.github] disable Windows/MSYS2 workflows for now by @stnolting in https://github.com/stnolting/neorv32/pull/424
Fix Critical Warning in Quartus 20.1.0: avoid power up to high by @akaeba in https://github.com/stnolting/neorv32/pull/423
litexcorecomplex: Expose configuration constants as generics. by @enjoy-digital in https://github.com/stnolting/neorv32/pull/425
Add HW reset to CPU counter CSRs by @stnolting in https://github.com/stnolting/neorv32/pull/426
:bug: [rtl] fix ispowerof_two VHDL function by @stnolting in https://github.com/stnolting/neorv32/pull/428
:bug: [sw/lib] fix UART "char_received" function by @stnolting in https://github.com/stnolting/neorv32/pull/431
[rtl] Optimize UART RTS behavior by @stnolting in https://github.com/stnolting/neorv32/pull/433
[rtl] Try to fix Quartus latch warnings by @stnolting in https://github.com/stnolting/neorv32/pull/434
✨ [sw] add assembly-only demo program by @stnolting in https://github.com/stnolting/neorv32/pull/436
[sw] rename blinkled example -> demoblink_led by @stnolting in https://github.com/stnolting/neorv32/pull/435
:warning: rework SPI module by @stnolting in https://github.com/stnolting/neorv32/pull/438
:warning: rework TWI module by @stnolting in https://github.com/stnolting/neorv32/pull/440
[rtl] minor rtl edits by @stnolting in https://github.com/stnolting/neorv32/pull/441
[rtl] rlt/code cleanups & optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/442

New Contributors

@enjoy-digital made their first contribution in https://github.com/stnolting/neorv32/pull/425

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.7.7...v1.7.8

- VHDL
Published by stnolting about 3 years ago

What's Changed

✨ Add 1-Wire Interface Controller by @stnolting in https://github.com/stnolting/neorv32/pull/402
[sw] remove 'register' qualifier by @stnolting in https://github.com/stnolting/neorv32/pull/404
[rtl] Cleanup hardware reset logic by @stnolting in https://github.com/stnolting/neorv32/pull/405
[rtl] minor edits and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/406
⚠️ [rtl] cleanup CPU standard counters, remove CPUCNTWIDTH generic by @stnolting in https://github.com/stnolting/neorv32/pull/407
[rtl] minor edits of FIFO module by @stnolting in https://github.com/stnolting/neorv32/pull/408
[rtl] set 'mtval' CSR to zero if illegal instruction exception by @stnolting in https://github.com/stnolting/neorv32/pull/409
[rtl] minor edits and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/410
🐛 [rtl] fix minor bug in mie CSR (FIRQs) by @stnolting in https://github.com/stnolting/neorv32/pull/411
:bug: [rtl] fix B ISA instruction decoding collisions by @stnolting in https://github.com/stnolting/neorv32/pull/413
Fix typo. by @ahmedcharles in https://github.com/stnolting/neorv32/pull/416
[rtl] XLEN cleanup by @stnolting in https://github.com/stnolting/neorv32/pull/417

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.7.6...v1.7.7

- VHDL
Published by stnolting over 3 years ago

What's Changed

change base address of BUSKEEPER by @stnolting in https://github.com/stnolting/neorv32/pull/385
[rtl] relocate TWI tri-state drivers by @stnolting in https://github.com/stnolting/neorv32/pull/386
[rtl] optimize instruction fetch by @stnolting in https://github.com/stnolting/neorv32/pull/387
[rtl/PWM] minor cleanup by @stnolting in https://github.com/stnolting/neorv32/pull/388
🔒 [TRNG] add read data security feature by @stnolting in https://github.com/stnolting/neorv32/pull/389
🚀 [sw] Update software framework to GCC 12.1.0 by @stnolting in https://github.com/stnolting/neorv32/pull/391
[rtl] minor edits and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/396
[sw} cleanup crt0 start-up code by @stnolting in https://github.com/stnolting/neorv32/pull/397
[rtl] core cleanup / minor fixes by @stnolting in https://github.com/stnolting/neorv32/pull/398
🚀 [docs] add neorv32-verilog repository by @stnolting in https://github.com/stnolting/neorv32/pull/400

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.7.5...v1.7.6

- VHDL
Published by stnolting over 3 years ago

What's Changed

🐛 [rtl] cycle & instret bug fix, wishbone.we bug fix; minor rtl updates by @stnolting in https://github.com/stnolting/neorv32/pull/367
:bug: [rtl] fix PMP config by @stnolting in https://github.com/stnolting/neorv32/pull/368
[rtl] minor edits and updates by @stnolting in https://github.com/stnolting/neorv32/pull/369
[ug] add new section "LiteX Support" by @stnolting in https://github.com/stnolting/neorv32/pull/370
🔒 Specifiy Physical Memory Attributes by @stnolting in https://github.com/stnolting/neorv32/pull/372
[rtl] add CUSTOM_ID generic by @stnolting in https://github.com/stnolting/neorv32/pull/374
[sw] add ISR based SPI data flow example by @akaeba in https://github.com/stnolting/neorv32/pull/373
⚠️ [linker script] simplify memory configuration by @stnolting in https://github.com/stnolting/neorv32/pull/375
:warning: [rtl] rework SLINK module by @stnolting in https://github.com/stnolting/neorv32/pull/377
[sw example] demospiirq can handle FIFO by @akaeba in https://github.com/stnolting/neorv32/pull/382
✨ [rtl] add optional SPI data FIFO by @stnolting in https://github.com/stnolting/neorv32/pull/381
[rtl] minor cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/383
[rtl] minor cleanup by @stnolting in https://github.com/stnolting/neorv32/pull/384

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.7.4...v1.7.5

- VHDL
Published by stnolting over 3 years ago

What's Changed

:bug: fix CPU stall on illegal LD/ST instruction by @stnolting in https://github.com/stnolting/neorv32/pull/356
🧪 [rtl/system_integration] add LiteX core complex wrapper by @stnolting in https://github.com/stnolting/neorv32/pull/353
[rtl] minor cleanups and typo fixes by @stnolting in https://github.com/stnolting/neorv32/pull/357
[rtl] add "cached access" infrastructure by @stnolting in https://github.com/stnolting/neorv32/pull/359
[image_generator, makefile] Update "raw" executable formats by @stnolting in https://github.com/stnolting/neorv32/pull/360
🧪 [XIP] add experimental burst mode; fix endianness by @stnolting in https://github.com/stnolting/neorv32/pull/361
🐛 [bootloader] fix flash byte-order by @stnolting in https://github.com/stnolting/neorv32/pull/362
Fix PMP locking by @stnolting in https://github.com/stnolting/neorv32/pull/363
[sw] update bootloader by @stnolting in https://github.com/stnolting/neorv32/pull/364
🐛 [PMP] rework and fixes by @stnolting in https://github.com/stnolting/neorv32/pull/365
[rtl] reset all "core" CSRs to zero by @stnolting in https://github.com/stnolting/neorv32/pull/366

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.7.3...v1.7.4

- VHDL
Published by stnolting over 3 years ago

What's Changed

:sparkles: Add watchdog pause flag by @stnolting in https://github.com/stnolting/neorv32/pull/331
[rtl] add hardware reset to IO/peripheral devices by @stnolting in https://github.com/stnolting/neorv32/pull/334
:bug: fix SPI & XIP clock phase offset by @stnolting in https://github.com/stnolting/neorv32/pull/336
[rtl] split executable images into package and body by @akaeba in https://github.com/stnolting/neorv32/pull/338
[rtl] rework TWI module by @stnolting in https://github.com/stnolting/neorv32/pull/340
[rtl] add Wishbone output "gating" by @stnolting in https://github.com/stnolting/neorv32/pull/344
[rtl] rework reset system by @stnolting in https://github.com/stnolting/neorv32/pull/345
⚠️ [rtl] rework SLINK module by @stnolting in https://github.com/stnolting/neorv32/pull/349
[rtl] minor clean-ups/optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/351
[rtl] add "async TX" Wishbone option by @stnolting in https://github.com/stnolting/neorv32/pull/352

New Contributors

@akaeba made their first contribution in https://github.com/stnolting/neorv32/pull/338

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.7.2...v1.7.3

🎉 Two years NEORV32! 😄

- VHDL
Published by stnolting over 3 years ago

What's Changed

:warning: remove CPU's A ISA extension (atomic memory access) by @stnolting in https://github.com/stnolting/neorv32/pull/308
Add further mxisa CSR flags by @stnolting in https://github.com/stnolting/neorv32/pull/309
:bug: fix bug in CPU counter overflow logic by @stnolting in https://github.com/stnolting/neorv32/pull/310
update to new neoTRNG v2 by @stnolting in https://github.com/stnolting/neorv32/pull/311
Cleanup bitmanip co-processor by @stnolting in https://github.com/stnolting/neorv32/pull/312
:bug: fix buskeeper timeout error by @stnolting in https://github.com/stnolting/neorv32/pull/315
[TRNG] add optional/configurable data FIFO by @stnolting in https://github.com/stnolting/neorv32/pull/316
🐛 fix XIP sub-word accesses by @stnolting in https://github.com/stnolting/neorv32/pull/320
crt0.S: Do not clear XIP control registers except in bootloader mode by @jpf91 in https://github.com/stnolting/neorv32/pull/318
[linker script, crt0] align all sections to 32-bit boundaries by @stnolting in https://github.com/stnolting/neorv32/pull/323
Constructors by @GideonZ in https://github.com/stnolting/neorv32/pull/324
🐛 Fix sync. vs. async. exception collision by @stnolting in https://github.com/stnolting/neorv32/pull/327
rework bootloader's SPI flash access by @stnolting in https://github.com/stnolting/neorv32/pull/321
Bugfix - eliminates potential shift of data by 4 bytes. by @GideonZ in https://github.com/stnolting/neorv32/pull/313
:bug: fix debugger single-instruction stepping mode by @stnolting in https://github.com/stnolting/neorv32/pull/329

New Contributors

@jpf91 made their first contribution in https://github.com/stnolting/neorv32/pull/318
@GideonZ made their first contribution in https://github.com/stnolting/neorv32/pull/324

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.7.1...v1.7.2

- VHDL
Published by stnolting over 3 years ago

What's Changed

Rework register file's "zero" register by @stnolting in https://github.com/stnolting/neorv32/pull/298
:broom: [rtl] CPU frontend cleanup by @stnolting in https://github.com/stnolting/neorv32/pull/299
[rtl] make CPU front-end synchronous by @stnolting in https://github.com/stnolting/neorv32/pull/300
[rtl] optimize CPU barrel shifter timing by @stnolting in https://github.com/stnolting/neorv32/pull/301
VHDL code clean-ups by @stnolting in https://github.com/stnolting/neorv32/pull/303
Processor check edits by @stnolting in https://github.com/stnolting/neorv32/pull/304
[rtl] optimize CPU mul/div unit by @stnolting in https://github.com/stnolting/neorv32/pull/305
✨ [rtl] add simple branch prediction by @stnolting in https://github.com/stnolting/neorv32/pull/306

ℹ️ See CHANGELOG.md for more details.

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.7.0...v1.7.1

- VHDL
Published by stnolting almost 4 years ago

What's Changed

Fix some typos. by @ahmedcharles in https://github.com/stnolting/neorv32/pull/286
Fix the link using an asciidoc trick. by @ahmedcharles in https://github.com/stnolting/neorv32/pull/288
[rtl] set mtval CSR to zero on ebreak instructions by @stnolting in https://github.com/stnolting/neorv32/pull/289
🧪 try to fix *reducef functions usage for gate-level simulation by @stnolting in https://github.com/stnolting/neorv32/pull/290
Typo. by @ahmedcharles in https://github.com/stnolting/neorv32/pull/287
Move riscv-arch-test tests into separate repository by @stnolting in https://github.com/stnolting/neorv32/pull/291
rework of CPU's issue engine by @stnolting in https://github.com/stnolting/neorv32/pull/292
[CPU] area and timing optimization; closing further illegal instruction holes by @stnolting in https://github.com/stnolting/neorv32/pull/293
[CPU] fixed/optimized (illegal) instruction dcoding logic by @stnolting in https://github.com/stnolting/neorv32/pull/294
add gate for CSR read address by @stnolting in https://github.com/stnolting/neorv32/pull/295
Rework C decompressor by @stnolting in https://github.com/stnolting/neorv32/pull/296
:bug: fix bug in crt0.S interrupt setup by @stnolting in https://github.com/stnolting/neorv32/pull/297

New Contributors

@ahmedcharles made their first contribution in https://github.com/stnolting/neorv32/pull/286

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.6.9...v1.7.0

- VHDL
Published by stnolting almost 4 years ago

What's Changed

[rtl/core] rework CPU data path by @stnolting in https://github.com/stnolting/neorv32/pull/279
🐛 [rtl/core] fix bug in mip CSR clear/acknowledge by @stnolting in https://github.com/stnolting/neorv32/pull/280
⚠️ Rework physical memory protection (PMP) [NAPOT -> TOR] by @stnolting in https://github.com/stnolting/neorv32/pull/281
Update neorv32_gptmr.c by @prdwivedi in https://github.com/stnolting/neorv32/pull/282
🐛 [PMP] fix pmpaddr CSR layout by @stnolting in https://github.com/stnolting/neorv32/pull/283
[rtl] CPU code clean-up; add RISC-V mstatus.TW CSR bit by @stnolting in https://github.com/stnolting/neorv32/pull/285

ℹ️ See CHANGELOG.md for more details.

New Contributors

@prdwivedi made their first contribution in https://github.com/stnolting/neorv32/pull/282

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.6.8...v1.6.9

- VHDL
Published by stnolting almost 4 years ago

What's Changed

✨[Zxcfu ISA ext.] add option to implement custom RISC-V instructions by @stnolting in https://github.com/stnolting/neorv32/pull/264
🐛 [sw] fixed bug in bootloader's (M)TIME handling by @stnolting in https://github.com/stnolting/neorv32/pull/267
:test_tube: Using LTO (link-time-optimization) for bootloader + console improvements by @stnolting in https://github.com/stnolting/neorv32/pull/268
[docs/datasheet] rework & update NEORV32 runtime environment (RTE) section by @stnolting in https://github.com/stnolting/neorv32/pull/272
[rtl] add err_o signal to IMEM modules by @stnolting in https://github.com/stnolting/neorv32/pull/273
✨ [rtl] on-chip debugger: add RISC-V trigger module for hardware breakpoints by @stnolting in https://github.com/stnolting/neorv32/pull/274
[sw] add support for newlib's system calls by @stnolting in https://github.com/stnolting/neorv32/pull/275
⚠️ replace SYSINFO.CPU memory-mapped register by custom "mxisa" CSR by @stnolting in https://github.com/stnolting/neorv32/pull/276
[OCD] stop CPU counters during debugging by @stnolting in https://github.com/stnolting/neorv32/pull/277
Add newlib example program and documentation by @stnolting in https://github.com/stnolting/neorv32/pull/278

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.6.7...v1.6.8

- VHDL
Published by stnolting about 4 years ago

What's Changed

[setups] move to repo neorv32-setups by @umarcor in https://github.com/stnolting/neorv32/pull/254
[rtl/core] rework CPU issue engine (area optimization) by @stnolting in https://github.com/stnolting/neorv32/pull/256
[DOC] User Guide - 1.3. Installation by @befedo in https://github.com/stnolting/neorv32/pull/258
[B ISA extension] add single-bit instructions (Zbs) support by @stnolting in https://github.com/stnolting/neorv32/pull/259
[B ISA extension] add carry-less multiply instructions (Zbc) support by @stnolting in https://github.com/stnolting/neorv32/pull/260
[CFS] add demo program by @stnolting in https://github.com/stnolting/neorv32/pull/261
[rtl/core] add 4 additional CPU CP slots; fix bugs in CP arbitration logic by @stnolting in https://github.com/stnolting/neorv32/pull/262
[sw] rework intrinsics (e.g. for custom instructions) by @stnolting in https://github.com/stnolting/neorv32/pull/263

New Contributors

@befedo made their first contribution in https://github.com/stnolting/neorv32/pull/258

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.6.6...v1.6.7 Project Changelog: CHANGELOG.md

- VHDL
Published by stnolting about 4 years ago

What's Changed

Fix compile error with questa, for issue #242 by @tmeissner in https://github.com/stnolting/neorv32/pull/243
⚠️ Make PWM and XIRQ IOs fixed-sized by @stnolting in https://github.com/stnolting/neorv32/pull/241
✨ Add Execute In Place (XIP) Module by @stnolting in https://github.com/stnolting/neorv32/pull/244
[rtl/core/mem] Rename legacy-style memory files by @stnolting in https://github.com/stnolting/neorv32/pull/246
[.github/riscv-arch-test] Fix / rework by @stnolting in https://github.com/stnolting/neorv32/pull/248
[BUSKEEPER] Add NULL address check option by @stnolting in https://github.com/stnolting/neorv32/pull/247
:warning: [XIP] reworked execute in place module by @stnolting in https://github.com/stnolting/neorv32/pull/249
[SPI & XIP] add high-speed SPI mode option by @stnolting in https://github.com/stnolting/neorv32/pull/251
setups/osflow/synthesis: recent versions of yosys need command 'read_verilog' by @umarcor in https://github.com/stnolting/neorv32/pull/252
🐛 [BUSKEEPER] fix bug in error flag logic by @stnolting in https://github.com/stnolting/neorv32/pull/253
[GPIO] raise bus exception if writing to INPUT registers by @stnolting in https://github.com/stnolting/neorv32/pull/255

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.6.5...v1.6.6

- VHDL
Published by stnolting about 4 years ago

What's Changed

Fix neorv32gpioport_get() by @hipolitoguzman in https://github.com/stnolting/neorv32/pull/223
[docs/userguide] split user guide into several files by @stnolting in https://github.com/stnolting/neorv32/pull/222
TRNG and Vivado block designs by @stnolting in https://github.com/stnolting/neorv32/pull/229
⚠️ Remove legacy SW (compatibility) wrappers by @stnolting in https://github.com/stnolting/neorv32/pull/228
:bug: Fix Wishbone timeout bug by @stnolting in https://github.com/stnolting/neorv32/pull/230
Add SYSINFO flag to check if processor is being simulated by @stnolting in https://github.com/stnolting/neorv32/pull/231
Add a System View Description (SVD) file by @stnolting in https://github.com/stnolting/neorv32/pull/225
⚠️ Rework FIRQ System (re-rework): use MIP to clear/ack IRQs by @stnolting in https://github.com/stnolting/neorv32/pull/236
[sw/example] add SLINK demo program by @stnolting in https://github.com/stnolting/neorv32/pull/235
📚 [SW makefile] add variables to help target by @stnolting in https://github.com/stnolting/neorv32/pull/237
MULDIV optimization by @stnolting in https://github.com/stnolting/neorv32/pull/238
Watchdog [WDT]: add option to enable/disable WDT during debugging by @stnolting in https://github.com/stnolting/neorv32/pull/239
[setups/osflow] update README by @stnolting in https://github.com/stnolting/neorv32/pull/221
Faster mul/div operations by @stnolting in https://github.com/stnolting/neorv32/pull/240

New Contributors

@hipolitoguzman made their first contribution in https://github.com/stnolting/neorv32/pull/223

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.6.4...v1.6.5

- VHDL
Published by stnolting about 4 years ago

Bug Fixes

fixed bug in WISHBONE interface: pipelined Wishbone mode did not clear STB after first transfer cycle
on-chip debugger: reworked JTAG signal input/output synchronization logic (#216) - JTAG signals were not correctly sampled at the right rising/falling clock edges

Updates and New Features

reworked TRNG (#212)
:warning: removed WICTRLCKSTEN flag (enable clock stretching) from control registers, clock-stretching is now always enabled
major control unit and AKU logic optimizations; :lock: closed further illegal instruction encoding holes (system environment instructions, ALU and ALU-immediate instructions, FENCE instructions) (#204)
:warning: reworked IRQ trigger logic of SPI, TWI, UART0, UART1, NELOED and SLINK; FIRQs now only trigger once when the programmed interrupt condition is met instead of triggering all the time (#202)
added new peripheral module - General Purpose 32-bit Timer GPTMR (#195)

What's Changed

Add a Gitter chat badge to README.md by @gitter-badger in https://github.com/stnolting/neorv32/pull/196
Add general purpose timer GPTMR by @stnolting in https://github.com/stnolting/neorv32/pull/195
Add cyclone2 legacy mem-files by @stnolting in https://github.com/stnolting/neorv32/pull/198
[ci] use option 'pacboy' to simplify workflow 'Windows' by @umarcor in https://github.com/stnolting/neorv32/pull/201
Rework peripheral's FIRQ triggering by @stnolting in https://github.com/stnolting/neorv32/pull/202
Added neorv32-examples by @emb4fun in https://github.com/stnolting/neorv32/pull/205
CPU logic optimization by @stnolting in https://github.com/stnolting/neorv32/pull/204
[TWI] remove clock-stretching enable flag by @stnolting in https://github.com/stnolting/neorv32/pull/209
setups/osflow/Makefile: support overriding variables by @umarcor in https://github.com/stnolting/neorv32/pull/214
Rework TRNG module by @stnolting in https://github.com/stnolting/neorv32/pull/212
Added a example serial terminal program for Linux by @qwqw330 in https://github.com/stnolting/neorv32/pull/215
[On-Chip Debugger] Fix JTAG timing by @stnolting in https://github.com/stnolting/neorv32/pull/216
Add iCEBreaker Board to the osflow by @lab-mathias-claussen in https://github.com/stnolting/neorv32/pull/217
Adding the possibility of indicate external sources throw a enviromen… by @zipotron in https://github.com/stnolting/neorv32/pull/213

New Contributors

@gitter-badger made their first contribution in https://github.com/stnolting/neorv32/pull/196
@emb4fun made their first contribution in https://github.com/stnolting/neorv32/pull/205
@qwqw330 made their first contribution in https://github.com/stnolting/neorv32/pull/215
@lab-mathias-claussen made their first contribution in https://github.com/stnolting/neorv32/pull/217

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.6.3...v1.6.4

- VHDL
Published by stnolting about 4 years ago

Bug Fixes

fixed bug in *_reduce_f VHDL functions (#186)
fixed imprecise illegal instructions exception (ALU-class operations); mepc and mtval did not present the correct exception-causing data

Updates and New Features

:warning: removed CPU_EXTENSION_RISCV_Zbb, added CPU_EXTENSION_RISCV_B generic (#190)
- all currently supported bit-manipulation sub-extensions are enabled/disabled by the CPU_EXTENSION_RISCV_B generic
- added support of Zba (address computation instructions) bit-manipulation sub-extension
added generics to explicitly enable Zicntr and Zihpm extensions (#192)
- CPU_EXTENSION_RISCV_Zicntr, true by default, implements basic CPU counter CSRs ([m]time, [m]cycle[h], [m]instret[h])
- CPU_EXTENSION_RISCV_Zihpm, false by default, implements hardware performance monitor CSRs
added memory-mapped register to BUSKEEPER to identify precise cause of bus access exceptions (#191)
bootloader now uses physical memory configuration (from SYSINFO) module to setup stack pointer
added option to configure clock polarity and clock phase of SPI module (#185)
minor logic optimizations (reducing area footprint and shortening critical path) and code clean-ups

What's Changed

[SPI] Add CPOL (clock polarity) configuration option by @stnolting in https://github.com/stnolting/neorv32/pull/185
fix: reduce_f won't work with single bit operands by @gottschalkm in https://github.com/stnolting/neorv32/pull/186
[setups/ULX3S] increase memory sizes to "default" by @stnolting in https://github.com/stnolting/neorv32/pull/188
[B ISA Extension] Rework and addition of Zba subset by @stnolting in https://github.com/stnolting/neorv32/pull/190
[BUSKEEPER] add memory-mapped status register by @stnolting in https://github.com/stnolting/neorv32/pull/191
RISC-V "Zicntr" and "Zihpm" extensions by @stnolting in https://github.com/stnolting/neorv32/pull/192

Closed Issues

#140 Usage of Logic Elements almost double when synthesizing for Max 10
#145 Radiant setup fails to build with Radiant 2.2.1.239.2
#169 SDRAM controller for the ULX3S
#181 neorv32/docs/userguide/content.adoc en dash / em dash

New Contributors

@gottschalkm made their first contribution in https://github.com/stnolting/neorv32/pull/186

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.6.2...v1.6.3

- VHDL
Published by stnolting over 4 years ago

neorv32 - v1.6.2

This list shows the main core changes since the last release. See the project's changelog for more information.

:bug: Bug Fixes

fixed signal and generic propagation in rtl/system_integration and setups/radiant/UPduino_v3

:bulb: Updates and New Features

:warning: changes handling of software makefile's MARCH and MABI variables (see #184): omitting -march and -mabi flags for these variables
:warning: reworked fast interrupt request (FIRQ) CPU system: FIRQs are now high-level-triggered and have to stay asserted until explicitly acknowledged (see #176)
:warning: removed mstatus.TW (timeout wait) CSR bit: wfi instruction is now always allowed to execute in less-privileged modes
:warning: removed sleep_i signal of custom functions subsystem (CFS)
:lock: CPU now ensures that all illegal instructions do not commit any potential architecture state changes
on-chip debugger: wfi now executes as nop when in debug-mode (also during single-stepping)
NEOLED: added new control register bit to configure interrupt condition
SLINK: added fine-grained per-link interrupt configuration (see #182)
UART0, UART1: added optional and configurable RX and TX FIFOs, added fine-grained IRQ configuration (see #183)
CPU logic, timing and area optimizations

:heavycheckmark: Pull Requests and Issues

Merged pull requests: * #170 🐛 [rtl/systemintegration] fix uart1 rx/tx signals * #173 Add argument to makefile to simplify Continuous Integration flow * #174 [setups/vivado] Mention the XHub Stores menu item for installing board support * #175 [setups/vivado] Fix fileset paths * #176 [rtl/core] make FIRQs level-triggered * #177 [docs/datasheet] Fix neoled register bits documentation * #178 [rtl/systemintegration] add NEOLED FIFO depth generic to AXI4 wrapper * #180 [docs/datasheet] fix neoled register table formatting * #182 [SLINK] add fine-grained IRQ configuration * #183 [UARTs] add RX & TX FIFOs * #184 ⚠️ [makefile] modify handling of MARCH and MABI variables

Closed issues: * #171 Make Check Fails (riscv32-unknown-elf-gcc is not found) * #181 neorv32/docs/userguide/content.adoc en dash / em dash

- VHDL
Published by stnolting over 4 years ago

neorv32 - v1.6.1

This list shows the main core changes since the last release. See the project's changelog for more information.

:bug: Bug Fixes

fixed bug in MTIME comparator logic (interrupt condition mtime >= mtimecmp was not always evaluated correctly)
fixed CPU's IRQ prioritization: (re-)enter debug mode interrupts have to be evaluated before all other interrupts
fixed missing IRQ signal assignments (MSW and XIRQ) in AXI4-lite top wrapper

:bulb: Updates and New Features

:warning: split processor-internal memory VHDL sources (IMEM and DMEM) into separated files (PR #151):
- entity-only (rtl/core/neorv32_*mem.entity.vhd) and default architecture-only (rtl/core/mem/neorv32_*mem.default.vhd)
:warning: Zifencei extension is now required for the on-chip debugger; executing fence.i without having the Zifencei extension enabled will now cause an illegal instruction exception
:warning: major change of low-level hardware access (memory-mapped registers) PR #158:
- now using struct-based access concept (IO module = struct, interface registers = members of struct) instead of #define single-pointers, format: NEORV32_<module_name>.<register_name>
- renamed all control registers and bits from *CT* to *CTRL*
- added sw/lib/include/neorv32_legacy.h compatibility layer (maps deprecated "defines" to according structs, provides old control register/bit names)
:warning: reworked CPU trap/exception system (in order to comply with RISC-V specs.):
- removed non-maskable interrupt (NMI, top signal nm_irq_i)
- reworked CPU trap prioritization (sync exceptions before debug mode enter exceptions before async exceptions)
- RISC-V interrupts (MTI, MSI, MEI) are now high-level-triggered and require to stay asserted until they are explicitly acknowledged
started porting the task management system to PyDoit PR #110
misa, mip and mtval CSRs are read-only; however, write accesses to these CSRs do not raise an illegal instruction exception (anymore)
added menvcfg[h] CSRs (only available if U ISA extension is enabled; not used yet - hardwired to zero, but required by RISC-V spec.)
reworked CPU/software handshake of external interrupt controller XIRQ to avoid "external IRQ -> CPU IRQ" race conditions
if CPU_CNT_WIDTH generic (actual width of [m]cycle and [m]instret counters) is less than 64 the remaining bits are now just hardwired to zero ignoring any write access instead of causing an exception

:heavycheckmark: Pull Requests and Issues

Merged pull requests: * #150 [sim] create subdir 'simple', avoid making a local copy of 'sw' and 'sim' * #151 [rtl/core] split dmem/imem entities and architectures to separated files * #152 Adding NEORV32 Qsys/Platform Designer component and AvalonMM Master Interface wrapper * #154 fix typo wbmema.cyc on sim example * #156 [docs/userguide] update section 'Simulating the Processor' * #158 rework low-level hardware access * #159 [setups/osflow/filesets] do not provide default NEORV32MEMSRC, require it to be explicitly set * #160 add pydoit to custom dockerfiles * #161 [containers] update from Debian Buster to Debian Bullseye * #162 [doit] add initial doit file; add task DeployToGitHubPages * #163 [doit] add task Documentation * #164 [doit] add task RunRISCVArchitectureTests * #165 [doit] add task BuildAndInstallSoftwareFrameworkTests * #166 docs: datasheet: socsysinfo: fix NEORV32SYSINFO.SOC bits description

Closed issues: * #153 simulation cycle signal of instruction memory

- VHDL
Published by stnolting over 4 years ago

neorv32 - v1.6.0

This list shows the main core changes since the last release. See the project's changelog for more information.

:bug: Bug Fixes

fixed bug in mret instruction (caused an exception if user mode was not implemented)
fixed missing flash_sdi_i in Radiant-related example setups and processor wrappers

:bulb: Updates and New Features

:warning: removed USER_CODE generic and according SYSINFO register
:warning: removed custom mzext CSR; moved all information flags to new SYSINFO_CPU register in SYSINFO module
:warning: removed mstatus.SD and mstatus.FS CSR flags
added new designated test setups: rtl/test_setups, :books: UG: General Hardware Setup
fixed Zifencei test of riscv-arch-test port
added flags to SYSINFO module to check FAST_SHIFT_EN and FAST_MUL_EN generics by software
:sparkles: added support for RISC-V Zbb extension (basic bit-manipulation operations); support via intrinsic library

:heavycheckmark: Pull Requests and Issues

Merged pull requests: * #136 [proposal] add rtl/testsetups * #137 Move osflow examples * #139 Added AlhambraII and ULX3S boards * #142 split rtl/templates folder * #143 SYSINFO documentation fixups * #144 [setups] add terasic cyclone v starter kit * #149 [setup/osflow/boards/index.mk] do not set GHDLPLUGIN_MODULE unconditionally

Closed issues: * #128 Do we really need wrappers for the top entity? * #132 Cannot fit on XC6SLX9 * #135 Missing documentation and Makefiles for iCE40 and ECP5 Lattice FPGAs * #138 common/common.mk : 144 main.elf Error 1 * #148 Windows workflow keeps failing

- VHDL
Published by stnolting over 4 years ago

neorv32 - v1.5.9

This list shows the main core changes since the last release. See the project's changelog for more information.

:bug: Bug Fixes

:warning: fixed major bug in CPU interrupt system: interrupts during memory accesses broke those memory accesses leading to undefined behavior
fixed bug in E ISA extension that prevented the extension to be actually enabled
fixed bug in linker script (#134): missing constant data section
fixed bug in AXI4-Lite wrapper (#133) that caused failure of Vivado packaging
fixed bug in execution of xRET instructions (trapping of MRET and DRET when not in according mode was missing)

:bulb: Updates and New Features

:warning: top entity machine-level interrupts now trigger on rising edges (mext_irq_i, msw_irq_i, mtime_irq_i, nm_irq_i)
exposed advanced external bus interface configuration options as new top entity generics (moved from package constants): MEM_EXT_PIPE_MODE, MEM_EXT_BIG_ENDIAN, MEM_EXT_ASYNC_RX
added mstatus.TW CSR flag (to allow execution of wfi in user machine mode)
added mstatus.FS and mstatus.SD CSR bits to control the state of the FPU (Zfinx extension)
added mconfigptr CSR (not actually used yet, read-only, always zero)
reworked CPU register file ("implementation" of zero register)
clean-up of processor top's generic and signals default values

:heavycheckmark: Pull Requests and Issues

Merged pull requests: * none

Closed issues: * #133 Problems generating a Vivado-Block Design * #134 Missing memory section for .rodata in neorv32.ld

- VHDL
Published by stnolting over 4 years ago

neorv32 - v1.5.8

This list shows the main core changes since the last release. See the project's changelog for more information.

:bug: Bug Fixes

fixed bug in custom functions subsystem CFS: address map layout overlapping
fixed minor bug in FIFO component (setups with FIFO_DEPTH = 1 caused mapping issues)

:bulb: Updates and New Features

added RISC-V Zmmul ISA extension (subset of M extension: integer HW multiplier, but no HW divider; intended for area-constrained setups)
bootloader is more independent of HW configuration (no need for UART, MTIME, GPIO anymore); added several options to customize default bootloader
:warning: removed top's fast IRQ (FIRQ) inputs soc_firq_i
:warning: removed numerically-controller oscillator module (NCO)
added new processor module stream link interface (SLINK) providing up to 8 independent RX and TX links
increased GPIO port size from 32-bit to 64-bit
added new processor module external interrupt controller (XIRQ) providing up to 32 processor-external interrupt request lines
new performance-vs-ares configuration generic: CPU_IPB_ENTRIES defines size of CPU's instruction prefetch buffer
reworked NEOLED module: IRQ now uses fifo half-full fill level; added option to send LED RESET command as explicit FIFO command
(re-)added mstatush CSR (hardwired to zero)
minor logic optimizations to reduce area requirements and switching activity and to shorten critical path

:heavycheckmark: Pull Requests and Issues

Merged pull requests: * #89 Make uartrx a verification component * #90 Make uartrx a VUnit verification component. Step 4. * #92 sim: update readme * #93 [setups/vivado] arty-a7-test-setup: define multiple filesets, set board, set language * #95 Add loopback test for SLINK * #98 OrangeCrab * #99 osflow rework * #100 [docs] move Makefile from project root to subdir 'docs' * #104 [setups/osflow] cleanup * #107 [setups/osflow] update OrangeCrab constraints file * #109 riscv-arch-test script cleanup * #114 use RISCVPREFIX instead of RISCVTOOLCHAIN * #116 [ci] add workflow 'Containers' * #117 mv riscv-arch-test sw/sig-arch-test * #118 [sw/example] add common.mk * #119 [riscv-arch-test] measure execution time of each test * #120 [sim/ghdl] use --workdir=build * #123 [docs] update references to isa-test * #124 Split ISA test suites in multiple jobs and rework makefiles * #125 Fix source/sink mixup in SLINK docs * #127 [ci/windows] fix RISCV_PREFIX

Closed issues:

#77 Use ProcessorTop templates in non osflow examples
#97 Having trouble building the iCESugar example
#106 Constraints file for OrangeCrab r0.2
#108 question: Is the prebuilt build support rv32IMAC ISA extension or just rv32imc?
#122 Add halfway interrupts for SLINK interface

- VHDL
Published by stnolting over 4 years ago

neorv32 - v1.5.7

This list shows the main changes since the last release. See the project's changelog for more information.

:bug: Bug Fixes

fixed bug in instruction cache flush/re-sync logic (via fence.i instruction) - cache might have missed a re-sync request in some cases
fixed bug in debugger park loop: instruction cache re-sync (fence.i) was missing - caused debugger to execute obsolete code from program buffer

:bulb: Updates and New Features

fixed endiannes inconsistencies: processor/CPU is little-endian
:warning: removed TINY_SHIFT_EN generic; CPU shifter is implemented as iterative single-bit shift by default
:warning: reworked boot configuration
- removed MEM_INT_IMEM_ROM generic; processor-internal IMEM is implemented as ROM if internal IMEM is enabled (MEM_INT_IMEM_EN = true) and internal bootloader is disabled (INT_BOOTLOADER_EN = false)
:warning: removed option to grant user-level access to HPM counters (removed according mcounteren CSR bits)
increased processor-internal IO size (from 256 bytes to 512 bytes)
- relocated base address of CFS module
number of PWM channels is now configured via IO_PWM_NUM_CH generic (0=none at all, max 60)
:warning: CPU B extension has been (temporarily) removed from the core
CPU_CNT_WIDTH and HPM_CNT_WIDTH generics can now also be zero to exclude CPU core counters (cycle & instret) and HPM counters
minor logic optimizations to reduce area requirements and switching activity and to shorten critical path

:heavycheckmark: Pull Requests and Issues

Merged pull requests: * #47 Update CI to use VUnit for running VHDL testbenches * #48 Introduce VUnit logging and checking * #53 docs: split User Guide * #54 [ci] cleanup * #59 Add examples * #60 [docs] add attrs.adoc and attrs.main.adoc * #61 Reorganise setups * #63 Add Fomu * #64 [sim] split UART logging component, make self-checking * #65 Add VUnit * #66 [sim/VUnit] support CLI argument for selecting the expected UART responses * #67 rename logical library 'iCE40UP' to 'iCE40' * #69 VUnit checking * #71 Add MSYS2 jobs to continuous integration workflows * #72 [ci/riscv-arch-test] make test script executable * #73 [sim] make ghdlsim.sh executable * #74 [ci/generate-job-matrix] fix UPduinov3 artifact (bitstream) extension * #75 iCESugar * #76 [setups/examples] add iCESugar Minimal * #79 add mailmap * #80 Added option to print a selected subset of information from processor… * #82 [sim] use custom VUnit loggers for better verbosity control * #83 [setups/osflow] support optionally using Verilog sources and add Fomu MixedLanguage example * #84 [setups/osflow/iCESugar] update PCF

Closed issues:

#50 Endianness inconsistency
#58 mtime_o could be instable
#62 Processor Boot Concept
#70 Passing argument to ghdl_sim.sh - bug?

:books: Documentation

reworked data sheet section Address Space
- added section Memory Configuration
- added section Boot Configuration
reworked and updated complete User Guide
typo and layout fixes

- VHDL
Published by stnolting over 4 years ago

neorv32 - nightly

:rocket: Up-to-date automatic builds of the documentation and project source packaging (see the assets).

NEORV32-nightly.pdf - Data Sheet, also available online
NEORV32_UserGuide-nightly.pdf - User Guide, also available online

- VHDL
Published by github-actions[bot] almost 5 years ago

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