Recent Releases of loom
loom - v0.13.2
Added
- arithmetic expression simplification with rewrite engine
- progress on templated synthesis to val-rdy interfaces as a first step for compiling higher level languages
- initial structuring of weaver, a high level language like go
- some basic tests for many of the libraries
- documentation for many of the libraries
- region, bound, and segment to petri nets as an extension of the iterator
Removed
- Cut the old ucs library out of the project, and moved variables into the sub languages for modularity
Fixed
- better runtime linking of Python to load the technology file
- performance issue with calendar queue in prs simulator
- Python
Published by nbingham1 8 months ago
loom - v0.11.1
Added
- Ghosts that annotate how transitions on a given conditional branch propagate into the rest of the state space
- Python is now loaded dynamically on demand with support for all versions of python3
Changed
- Cleaned up debug messages and hooked up the debug flag as needed
- Python
Published by nbingham1 about 1 year ago
loom - v0.10.3
Fixed
- route lowering bug
- group constraints bug
- stack linkage bug
- multiple transistor models in one stack
- gate separation bug
- well label bug
- polygons in GDS import
Changed
- min width rule now a full DRC rule
Added
- cell import (still some bugs)
- tech directory management
- Python
Published by nbingham1 over 1 year ago
loom - v0.10.2
2564 of 2680 cells (95.7%) from the skywater cell library are now DRC and LVS clean. 22 minutes and 55 seconds to complete the run (0.5s per cell).
Fixed
- cleaning up virtual pin placement
- adding gate alignment metric into placer
- make cell hashing algorithm sensitive to full cell structure
- diffusion base net
- route draw to pin
- pin positioning
- route lo/hi setting
- gate extraction
- lock pin constraints
- Python
Published by nbingham1 over 1 year ago
loom - v0.10.0
Added
- spice extraction from layout with "undo" command
- layout versus schematic with "compare" command
- combine devices before canonicalization
Fixed
- pins placed properly in layout
- transistor base now labelled properly
- netlist canonicalization, now insensitive to source/drain order and sensitive to gate, base, and transistor size
Changed
- simplified UI and help text
- Python
Published by nbingham1 over 1 year ago
loom - v0.8.0
Added
- Automatic device-level sizing
- Export to spice netlist, this connects synthesis of behavioral spec down to layout
- Automatic keepers can now avoid the half-cycle timing assumption by adding two transistors if there isn't already one.
In Progress
- chpsim needs some work done in the arithmetic library.
- state variable insertion still needs some more work on the theoretical side.
- Python
Published by nbingham1 over 1 year ago
loom - v0.7.0
Added
- keepers are now automatically added
- simulation now generate a vcd file
Changed
- fixed import and export of production rule attributes
In Progress
- chpsim needs some work done in the arithmetic library.
- state variable insertion still needs some more work on the theoretical side.
- Python
Published by nbingham1 over 1 year ago
loom - v0.6.0
Added
- production rule simulation is now a device level simulation.
- support added for shared gate networks, pass transistor logic, weak drivers, delay assumptions, floating nets, proper instability propagation, etc.
- production rules now support sizing.
Changed
- prsim is now much faster, using Rete Algorithm and Calendar Queues.
In Progress
- chpsim needs some work done in the arithmetic library.
- state variable insertion still needs some more work on the theoretical side.
- Python
Published by nbingham1 over 1 year ago
loom - v0.5.0
Added
- Merged automated cell layout from Floret into Haystack. The main build command can now read spice files, and the parser is faster than Floret's.
Changed
- hsesim now uses a pareto distribution of random delays instead of random order of transitions. This makes it more likely to hit out of the way states and discover issues.
In Progress
- chpsim needs some work done in the arithmetic library.
- state variable insertion still needs some more work on the theoretical side.
- Python
Published by nbingham1 over 1 year ago
loom - v0.3.1
Release v0.3.1
hsesim
- Properly handles vacuous transitions through multi-branch selection statements.
hseenc
- Can solve state conflict problems for a much larger class of circuits at the expense of compile time.
- Various bug fixes throughout the conflict identification code.
- Python
Published by nbingham1 over 1 year ago