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iob-cache

Verilog Configurable Cache

https://github.com/iobundle/iob-cache

Science Score: 57.0%

This score indicates how likely this project is to be science-related based on various indicators:

  • ✓
    CITATION.cff file
    Found CITATION.cff file
  • ✓
    codemeta.json file
    Found codemeta.json file
  • ✓
    .zenodo.json file
    Found .zenodo.json file
  • ✓
    DOI references
    Found 2 DOI reference(s) in README
  • ○
    Academic publication links
  • ○
    Academic email domains
  • ○
    Institutional organization owner
  • ○
    JOSS paper metadata
  • ○
    Scientific vocabulary similarity
    Low similarity (11.9%) to scientific vocabulary
Last synced: 6 months ago · JSON representation ·

Repository

Verilog Configurable Cache

Basic Info
  • Host: GitHub
  • Owner: IObundle
  • License: mit
  • Language: Verilog
  • Default Branch: main
  • Homepage:
  • Size: 3.05 MB
Statistics
  • Stars: 175
  • Watchers: 7
  • Forks: 36
  • Open Issues: 6
  • Releases: 1
Created almost 6 years ago · Last pushed about 1 year ago
Metadata Files
Readme License Citation

README.md

IOb-cache

IOb-cache is a high-performance, configurable open-source Verilog cache. If you use or like this repository, please cite the following article: Roque, J.V.; Lopes, J.D.; Véstias, M.P.; de Sousa, J.T. IOb-Cache: A High-Performance Configurable Open-Source Cache. Algorithms 2021, 14, 218. https://doi.org/10.3390/a14080218

IOb-cache supports pipeline architectures, allowing one request per clock cycle (read and write). IOb-cache has both Native (pipelined) and AXI4 back-end interfaces. The Write Policy is configurable: either write-through/not-allocate or write-back/allocate. The configuration supports the number of ways, address width, cache's word size (front-end data width), the memory's word size (back-end data width), the number of lines and words per line, replacement policy (if set associative), and cache-control module (allows performance measurement, cache invalidation, and write-through buffer status).

Setup using Py2hwsw

IOb-Cache uses Py2hwsw to generate the hardware and software components. To install Py2hwsw, follow the instructions in the Py2hwsw repository. The file iob_cache.py is IOb-Cache's Py2hwsw description, which you can update to your needs.

Edit the Makefile file to set the back-end interface type (BEIF) and width (BEDATA_W) according to your needs at compile time. These variables can also be passed at the command line. You can also change the SIMULATOR variable used to select a specific simulator or the DOC variable used to choose a document type to generate. The Makefile provides the following targets for simulation, FPGA synthesis, and documentation generation.

Owner

  • Name: IObundle, Lda
  • Login: IObundle
  • Kind: organization

Custom Computing Machines

Citation (CITATION.cff) 

cff-version: 1.2.0
message: "If you use this software, please cite it as below. If you are an author, submit a pull request to add your name"
authors:
- family-names: "Roque"
  given-names: "Joao"
- family-names: "T. de Sousa"
  given-names: "Jose"
  orcid: "https://orcid.org/0000-0001-7525-7546"
title: "IOb-Cache"
version: 0.1.0
doi: 10.3390/a14080218
date-released: 2020-07-20
url: "https://github.com/github-linguist/linguist"

GitHub Events

Total
  • Watch event: 19
  • Delete event: 1
  • Push event: 3
  • Pull request event: 1
  • Fork event: 5
Last Year
  • Watch event: 19
  • Delete event: 1
  • Push event: 3
  • Pull request event: 1
  • Fork event: 5

Dependencies

.github/workflows/ci.yml actions
  • actions/checkout v3 composite