virtual-bus

Simple protocol to connect two memory mapped buses (e.g. for Hardware In The Loop)

https://github.com/agra-uni-bremen/virtual-bus

Science Score: 52.0%

This score indicates how likely this project is to be science-related based on various indicators:

✓
CITATION.cff file
Found CITATION.cff file
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codemeta.json file
Found codemeta.json file
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.zenodo.json file
Found .zenodo.json file
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DOI references
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Academic links in README
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Academic email domains
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Institutional organization owner
Organization agra-uni-bremen has institutional domain (agra.informatik.uni-bremen.de)
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JOSS paper metadata
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Scientific vocabulary similarity
Low similarity (0.4%) to scientific vocabulary

Last synced: 7 months ago · JSON representation ·

Repository

Simple protocol to connect two memory mapped buses (e.g. for Hardware In The Loop)

Basic Info

Host: GitHub
Owner: agra-uni-bremen
Language: C++
Default Branch: master
Size: 66.4 KB

Statistics

Stars: 0
Watchers: 9
Forks: 0
Open Issues: 1
Releases: 0

Created over 3 years ago · Last pushed over 1 year ago

Metadata Files

Citation

Owner

Name: agra-uni-bremen
Login: agra-uni-bremen
Kind: organization

Website: https://agra.informatik.uni-bremen.de/
Repositories: 53
Profile: https://github.com/agra-uni-bremen

Citation (CITATION.cff)

# This CITATION.cff file was generated with cffinit.
# Visit https://bit.ly/cffinit to generate yours today!

cff-version: 1.2.0
title: virtual-bus
message: >-
  If you want to cite this software, please use the metadata from this file.
type: software
authors:
  - given-names: Sallar
    family-names: Ahmadi-Pour
    email: sallar@uni-bremen.de
    affiliation: University of Bremen
    orcid: 'https://orcid.org/0000-0003-4000-6207'
  - given-names: Pascal
    family-names: Pieper
    email: pascal@pieper.de
    affiliation: German Aerospace Center - DLR e.V.
    orcid: 'https://orcid.org/0000-0002-7155-2537'
  - given-names: Rolf
    family-names: Drechsler
    email: drechsler@uni-bremen.de
    affiliation: University of Bremen
    orcid: 'https://orcid.org/0000-0002-9872-1740'
identifiers:
  - type: doi
    value: arXiv:2311.00442
    description: >-
      Virtual-Peripheral-in-the-Loop : A Hardware-in-the-Loop Strategy to Bridge the VP/RTL Design-Gap
repository-code: 'https://github.com/agra-uni-bremen/vpil-hw/'
abstract: >-
  Virtual-Peripheral-in-the-Loop : A Hardware-in-the-Loop Strategy to Bridge the VP/RTL Design-Gap 
license: MIT

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