radix2-fft-vhdl
VHDL implementation of radix2 fft pipeline algorithm for IEEE-754 single precision floating point data format
Science Score: 54.0%
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Repository
VHDL implementation of radix2 fft pipeline algorithm for IEEE-754 single precision floating point data format
Basic Info
- Host: GitHub
- Owner: bugratufan
- Language: VHDL
- Default Branch: master
- Size: 1.08 MB
Statistics
- Stars: 8
- Watchers: 1
- Forks: 2
- Open Issues: 0
- Releases: 0
Metadata Files
README.md
Radix-2 FFT - VHDL Implementation
Discrete-time Fourier transform (DFT) plays an important role in the analysis, design, and implementation of discrete-time signal processing algorithms and systems, and in signal processing applications such as linear filtering, correlation analysis, and spectrum analysis. The main reason behind DFT's importance is the existence of efficient algorithms used to calculate DFT.
In this project, the FFT algorithm is used to calculate the DFT of the input signal. FFT ignores non-repeating signals and determines periodic ones among complex signals and separates them into harmonic components.
With the RADIX2 Module created within the scope of this project, it is aimed to perform the fast fourier transform process by making 16-point sampling. Radix-2 FFT method was used in FFT calculations[1].
The system has 16 inputs in the IEEE-754 standard, each of which consists of 32 bits. The sampled signal value must be entered into these inputs. The results of the FFT process come out in the IEEE-754 32bit standard. Complex numbers are output as 2 pieces of IEEE-754 32bit standard, one for the complex part and one for the real part.
EXPECTED INCORRECT RESULTS
In some cases where the result is 0, it can give results very close to zero.
REFERENCES
[1] Ze-ke Wang, Xue Liu, “A combined SDC-SDF architecture for normal I/O pipelined radix-2 FFT”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, May 2014.
This IEEE-754 multiplication module used in the design: https://www.edaboard.com/showthread.php?52628-FLOATING-POINT-MULTIPLICATION-USING-VHDL
USEFUL ARTICLES AND LINKS
Nandyala Ramanatha Reddy, Lyla B. Das, A.Rajesh, Sriharsha Enjapuri, Dept. of Electronics and Communication, NIT Calicut, Calicut, India, “ASIC Implementation of High speed Fast Fourier Transform Based on Split-Radix algorithm”, International Conference on Embedded Systems, 2014
754-2008 - IEEE Standard for Floating-Point Arithmetic - IEEE Standard. [online] Available at: https://ieeexplore.ieee.org/document/4610935.
https://www.beechwood.eu/fft-implementation-r2-dit-r4-dif-r8-dif/
https://www.algorithm-archive.org/contents/cooleytukey/cooleytukey.html
Owner
- Name: Buğra Tufan
- Login: bugratufan
- Kind: user
- Location: Munich, Germany
- Company: Rohde & Schwarz
- Repositories: 1
- Profile: https://github.com/bugratufan
Ms. Student at Koç University | FPGA Development Engineer at Rohde & Schwarz
Citation (CITATION.cff)
cff-version: 1.2.0 message: "If you use this software, please cite it as below." authors: - family-names: "Tufan" given-names: "Buğra" orcid: "https://orcid.org/0000-0002-4777-9854" title: "Radix-2 FFT Implementation in VHDL" version: 1.0 date-released: 2029-09-03 url: "https://github.com/bugratufan/radix2-fft-vhdl"
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