aes_encrypt_core
VHDL implementation of 128-bit AES Encryption Core
Science Score: 44.0%
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Low similarity (10.1%) to scientific vocabulary
Repository
VHDL implementation of 128-bit AES Encryption Core
Basic Info
- Host: GitHub
- Owner: bugratufan
- License: gpl-3.0
- Language: VHDL
- Default Branch: master
- Size: 435 KB
Statistics
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
- Releases: 0
Metadata Files
README.md
AES Encryption Core
This repository contains a VHDL implementation of a 128-bit AES Encryption Core.
Overview
The Advanced Encryption Standard (AES) is a symmetric encryption algorithm established by the U.S. National Institute of Standards and Technology (NIST). This repository provides an implementation of the 128-bit AES Encryption Core written in VHDL.
Getting Started
To use this AES Encryption Core, clone this repository to your local machine. Ensure you have a VHDL compiler installed to compile and run the code.
Features
The AES Encryption Core offers the following features:
128-bit AES Encryption: The core function of this repository is to provide a VHDL implementation of the 128-bit Advanced Encryption Standard (AES) encryption algorithm.
Modular Design: The design of the AES core is modular, with separate VHDL files for each major component of the AES algorithm. This includes separate modules for adding round keys, creating round keys, performing the substitution bytes operation, shifting rows, and mixing columns.
Test Bench: The repository includes a test bench (
tb_aes_core.vhd) for the AES core, allowing for testing and validation of the encryption process.
Usage
To use the AES Encryption Core, follow these steps:
- Clone the repository to your local machine.
- Open the VHDL files in your preferred VHDL editor or integrated development environment (IDE).
- The main AES core is contained in
aes_core.vhd. This file integrates all the other modules (add_round_key.vhd,create_round_key.vhd,sbox_block.vhd,shift_rows.vhd,mix_column_block.vhd) to perform the AES encryption. - The
tb_aes_core.vhdfile can be used to test the AES core. This test bench applies test vectors to the AES core and checks the output against the expected results.
License
This project is licensed under the GPL-3.0 License. See the LICENSE file for more details.
Owner
- Name: Buğra Tufan
- Login: bugratufan
- Kind: user
- Location: Munich, Germany
- Company: Rohde & Schwarz
- Repositories: 1
- Profile: https://github.com/bugratufan
Ms. Student at Koç University | FPGA Development Engineer at Rohde & Schwarz
Citation (CITATION.cff)
cff-version: 1.2.0 message: "If you use this software, please cite it as below." authors: - family-names: "Tufan" given-names: "Buğra" orcid: "https://orcid.org/0000-0002-4777-9854" title: "VHDL implementation of a 128-bit AES Encryption Core" version: 1.0 date-released: 2022-02-25 url: "https://github.com/bugratufan/aes_encrypt_core"