https://github.com/agra-uni-bremen/vpil-hw

Hardware Description for VPiL (Virtual Prototype in the Loop)

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Hardware Description for VPiL (Virtual Prototype in the Loop)

Created over 1 year ago · Last pushed over 1 year ago

Readme License

This repository contains the hardware description for the work "Towards Hardware-in-the-Loop for Virtual Prototypes and RTL with VPiL".

The VPiL bus protocol can be found at in a co-existing repository for modularity, as the protocol is not bound to this specific hardware description or the RISC-V VP in particular.

Details of the implementation are partially described in this preprint.