airisc_core_complex - v1.3.0

HW

• fixed bug in pipeline's RAW conflict detection when F ISA extension is disabled
• add RISC-V mcountinhibit CSR
• fixed bug in interrupt system; the external interrupt request lines of the CPU trigger now on rising edges
• update SPI module adding control options for automatic chip-select during block transfers
• add optional true-random number generator (TRNG) SoC sub-module
• add support for fence.tso instruction (executed as NOP)
• several rtl updates, cleanups and optimizations
• add CMOD A7 FPGA setup
• fix bug in JALR instruction decoding (offset generation)

SW

• fixed bug in generation of MEM files - initialization of certain sections was missing
• added missing sections to linker script
• made linker script memory layout configurable via makefile commands
• update default example program

Docu

• cleanup, rework and update of documentation
• update core complex block diagram

- Verilog
Published by crolfes over 2 years ago

airisc_core_complex - v1.2.0

HW - fix interrupt issues - rework CPU pipeline front-end (instruction fetch) - re-add support for compressed instructions (RISC-V C ISA extension) - re-add instruction prefetch buffer - add Arty A7 setup, scripts and pre-built bitstream - add SIMD bitstream for Nexys Video

SW - add software HAL for SIMD/AI - add timer to minimal example program

Docu - add synthesis results FPGA to Readme: Nexys Video (Xilinx)

- Verilog
Published by crolfes about 3 years ago

airisc_core_complex - v1.1.0

• fixed several bugs (mainly in the memory module and the debug module)
• added board-support-package
  • reworked HAL
  • added Makefile-based application compilation
  • added simple example program (+ pre-compiled ELF executable)
• added RISC-V-compatible floating-point unit implementing the F ISA extension
• code and repository cleanups

- Verilog
Published by crolfes about 3 years ago