https://github.com/cad-polito-it/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more for CAD group's servers
https://github.com/cad-polito-it/hammer
Hammer: Highly Agile Masks Made Effortlessly from RTL
https://github.com/cad-polito-it/dnn-benchmarks
This repository is a comprehensive collection of benchmarks for Deep Neural Networks (DNNs), designed to evaluate and compare the performance of various models across different hardware configurations, frameworks, and datasets.
https://github.com/cad-polito-it/cv32e40p_tftlab
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
https://github.com/cad-polito-it/pulpino_testing
SBST/FuSa environment for Pulpino - An open-source microcontroller system based on RISC-V
https://github.com/cadam00/priorcon
Graph Community Detection Methods into Systematic Conservation Planning
https://github.com/cadet/cadet-workshop
Training materials of the CADET-Workshop for tutorials and self-study.
https://github.com/cadet/rdm-example-rectangular-pulse
CADET case study from paper: Analytical solutions and moment analysis of general rate model for linear liquid chromatography” (Shamsul Qamar et al.)
https://github.com/cadet/rdm-example-multi-state-steric-mass-action
CADET case study from paper: Multi-state steric mass action model and case study on complex high loading behavior of mAb on ion exchange tentacle resin (Diedrich et al.)