Projects

Projects

Updated 11 months ago

https://github.com/cornell-zhang/eqmap • Science 26%

Using e-graphs for logic synthesis

compiler egg fpga rtl rust synthesis verilog yosys

Updated 11 months ago

stereo_vision_core • Science 49%

Stereo Vision Core accelerator is a real-time stream processing architecture that calculates the disparity map of stereo images. The accelerator is available as an RTL description using VHDL, which is fully parametrizable and synthetizable for FPGA or ASIC.

accelerator disparity-map fpga image-processing robotics stereo-vision vhdl yosys

ecosyste.ms

Data

Tools

Indexes

Applications

Experiments

Open Source Science

https://github.com/cornell-zhang/eqmap • Science 26%

stereo_vision_core • Science 49%