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verilator • Rank 15.3 • Science 54%

Verilator open-source SystemVerilog simulator and lint system

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neotrng • Science 54%

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

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RMarkdown templates and ggplot themes for RTL Languages

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proteus • Science 44%

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

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microrv32 • Science 39%

SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype