https://github.com/dineshpinto/timetagger
FPGA programming for nanosecond photon counting
https://github.com/catarinaacsilva/md5-hardware
System based on hardware (FPGA) and software to implement MD5 Cryptographic Hash Function
enso-nic
Ensō is a high-performance streaming interface for NIC-application communication.
https://github.com/cornell-zhang/allo
Allo: A Programming Model for Composable Accelerator Design
neotrng
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
https://github.com/b1f6c1c4/deep-darkfantasy
Global Dark Mode for ALL apps on ANY platforms.
https://github.com/cornell-zhang/hcl-dialect
HeteroCL-MLIR dialect for accelerator design
https://github.com/cornell-zhang/heterocl
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
https://github.com/beehive-lab/protonvm
Parallel Bytecode Interpreter For Heterogeneous Hardware
https://github.com/ahp-electronics/fpga-template
Lattice FPGA Verilog project template
airisc_core_complex
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
https://github.com/berkeleylab/marble
Dual FMC FPGA carrier board developed for general purpose use in particle accelerator electronics instrumentation.
stereo_vision_core
Stereo Vision Core accelerator is a real-time stream processing architecture that calculates the disparity map of stereo images. The accelerator is available as an RTL description using VHDL, which is fully parametrizable and synthetizable for FPGA or ASIC.
https://github.com/crossroadsfpga/enso_eval
Artifact for the OSDI '23 paper: "Ensō: A Streaming Interface for NIC-Application Communication"
https://github.com/beehive-lab/fastpath_mp
FastPath_MP: An FPGA-based multi-path architecture for direct access from FPGA to NVMe SSD
neorv32
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.