Updated 10 months ago

ncnn • Rank 27.7 • Science 54%

ncnn is a high-performance neural network inference framework optimized for the mobile platform

Updated 10 months ago

https://github.com/cad-polito-it/ase_riscv_gem5_sim • Science 13%

RISCV Gem5 simulator flow for Architetture dei Sistemi di Elaborazione

Updated 10 months ago

symex-vp • Science 65%

A concolic testing engine for RISC-V embedded software with support for SystemC peripherals

Updated 10 months ago

core-v-mcu • Science 54%

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Updated 10 months ago

airisc_core_complex • Science 36%

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

Updated 10 months ago

neorv32 • Science 49%

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Updated 10 months ago

seal5 • Science 62%

Seal5 - Semi-automated LLVM Support for RISC-V Extensions including Autovectorization

Updated 10 months ago

aps • Science 44%

Методические материалы по разработке процессора архитектуры RISC-V

Updated 10 months ago

proteus • Science 44%

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

Updated 10 months ago

microrv32 • Science 39%

SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype

Updated 10 months ago

https://github.com/agra-uni-bremen/binsym • Science 26%

Symbolic execution for RISC-V machine code based on the formal LibRISCV ISA model

Updated 10 months ago

cv32e40p • Science 57%

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Updated 10 months ago

pulpino-top-level-cw305 • Science 44%

The top-level Verilog files for the CW305 to run and communicate with the RISC-V PULPINO core