ncnn
ncnn is a high-performance neural network inference framework optimized for the mobile platform
https://github.com/cad-polito-it/ase_riscv_gem5_sim
RISCV Gem5 simulator flow for Architetture dei Sistemi di Elaborazione
symex-vp
A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
core-v-mcu
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
airisc_core_complex
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
neorv32
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
https://github.com/agra-uni-bremen/binsym
Symbolic execution for RISC-V machine code based on the formal LibRISCV ISA model
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
pulpino-top-level-cw305
The top-level Verilog files for the CW305 to run and communicate with the RISC-V PULPINO core